yosys/techlibs
Marcelina Kościelnicka be9595e18f xilinx: Add RAMB4* blackboxes 2022-03-21 13:11:52 +01:00
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achronix Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
anlogic Removed dbits 8 since 9 will always be picked 2022-01-19 08:51:25 +01:00
common Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
coolrunner2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
easic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ecp5 ecp5: Do not use specify in generate in cells_sim.v. 2022-02-21 17:52:31 +01:00
efinix Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
gatemate synth_gatemate Revert cascade A/B port mixup 2021-11-13 21:53:25 +01:00
gowin gowin: add support for Double Data Rate primitives 2022-03-14 23:14:21 +01:00
greenpak4 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40 Fixed Verific parser error in ice40 cell library 2021-10-19 12:33:18 +02:00
intel Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
intel_alm intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
machxo2 iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
nexus nexus: Fix arith_map CO signal. 2022-02-06 13:05:30 +01:00
quicklogic Fix the help message of synth_quicklogic. 2022-01-31 02:23:59 +08:00
sf2 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
xilinx xilinx: Add RAMB4* blackboxes 2022-03-21 13:11:52 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00