yosys/techlibs/common
Eddie Hung 0b6d47f8bf Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Makefile.inc Add mul2dsp multiplier splitting rule and ECP5 mapping 2019-07-08 18:42:09 +01:00
adff2dff.v Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib Added cells.lib 2015-01-16 15:50:42 +01:00
cmp2lut.v cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
mul2dsp.v Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v Fix typo. 2018-12-05 17:13:27 +00:00
simlib.v Improve $specrule interface 2019-04-23 22:57:10 +02:00
synth.cc Make doc consistent 2019-06-14 10:32:46 -07:00
techmap.v Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00