mirror of https://github.com/YosysHQ/yosys.git
b9c98e0100
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:
module top(input a, input b, input clk_, output reg o, output o2);
wire clk;
BUFG bufg0 (
.I(clk_),
.O(clk),
);
always @(posedge clk)
o = a ^ b;
assign o2 = a ^ b;
endmodule
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|---|---|---|
| .. | ||
| Makefile.inc | ||
| cells_counter_map.v | ||
| cells_latch.v | ||
| cells_sim.v | ||
| coolrunner2_fixup.cc | ||
| coolrunner2_sop.cc | ||
| synth_coolrunner2.cc | ||
| tff_extract.v | ||
| xc2_dff.lib | ||