yosys/techlibs/common
Marcelina Kościelnicka 817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Makefile.inc abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
abc9_map.v abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 2020-05-14 16:44:35 -07:00
abc9_model.v abc9_ops/xaiger: further reducing Module::derive() calls by ... 2020-05-14 10:33:57 -07:00
abc9_unmap.v abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
adff2dff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib Added cells.lib 2015-01-16 15:50:42 +01:00
cmp2lcu.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cmp2lut.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
dff2ff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
gate2lut.v Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
gen_fine_ffs.py simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
mul2dsp.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
prep.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
simcells.v simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
simlib.v Add new builtin FF types 2020-06-23 15:40:02 +02:00
synth.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
techmap.v Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00