yosys/kernel
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL.
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
..
bitpattern.h Removed unnecessary cast. 2015-09-01 12:40:36 +02:00
calc.cc Fix mingw compile issue (2nd attempt) 2017-02-23 14:21:02 +01:00
cellaigs.cc Fixes for OAI4 cell implementation 2019-04-23 17:54:00 +01:00
cellaigs.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
celledges.cc Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
celledges.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
celltypes.h Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
consteval.h Move ConstEvalAig to aigerparse.cc 2019-06-13 16:28:11 -07:00
cost.h Refactor kernel/cost.h definition into cost.cc 2019-02-08 13:58:20 -08:00
driver.cc fix codestyle formatting 2019-04-29 19:20:33 +09:00
hashlib.h Add hashlib "<container>::element(int n)" methods 2019-03-14 22:04:42 +01:00
log.cc Fixes and cleanups in AST_TECALL handling 2019-06-07 12:41:09 +02:00
log.h Initial implementation of elaboration system tasks 2019-05-03 03:10:43 +03:00
macc.h Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
modtools.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
register.cc Add a few more filename rewrites 2019-06-20 10:27:59 -07:00
register.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
rtlil.cc Undo iterator based Module::remove() for cells, as containers will not 2019-06-27 15:03:21 -07:00
rtlil.h Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
satgen.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
sigtools.h SigMap performance improvement 2016-02-01 10:10:20 +01:00
utils.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
yosys.cc Use Pass::call_on_module() as per @cliffordwolf comments 2019-07-02 08:20:37 -07:00
yosys.h Optimize ceil_log2 function 2019-05-07 12:17:56 -05:00