Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL ... As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser		2020-04-27 09:44:24 -07:00
..
aiger	aigerparse: only define __STDC_FORMAT_MACROS it not already before.	2020-04-07 12:50:31 -07:00
ast	Preserve 'signed'-ness of a verilog wire through RTLIL	2020-04-27 09:44:24 -07:00
blif	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
ilang	Preserve 'signed'-ness of a verilog wire through RTLIL	2020-04-27 09:44:24 -07:00
json	Update JSON front-end to process new attr/param encoding	2019-08-01 12:48:22 +02:00
liberty	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
rpc	ast, rpc: record original name of $paramod\* as \hdlname attribute.	2020-04-18 03:47:28 +00:00
verific	verific: do not assert if wire not found; warn instead	2020-04-23 16:28:11 -07:00
verilog	Set Verilog source location for explicit blocks (`begin` ... `end`).	2020-04-17 06:23:03 +00:00