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yosys/frontends/ilang
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Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL 
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
 		2020-04-27 09:44:24 -07:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Add "make coverage" 2018-08-27 14:22:21 +02:00
ilang_frontend.cc Add "read_ilang -lib" 2019-04-05 17:31:49 +02:00
ilang_frontend.h Add "read_ilang -lib" 2019-04-05 17:31:49 +02:00
ilang_lexer.l read_ilang: improve style. NFC. 2020-04-06 18:31:15 +00:00
ilang_parser.y Preserve 'signed'-ness of a verilog wire through RTLIL 2020-04-27 09:44:24 -07:00