Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL ... As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser		2020-04-27 09:44:24 -07:00
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Makefile.inc	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
ast.cc	ilang, ast: Store parameter order and default value information.	2020-04-21 19:09:00 +02:00
ast.h	Add LookaheadRewriter for proper bitselwrite support	2020-04-16 12:11:07 +02:00
dpicall.cc	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
genrtlil.cc	Preserve 'signed'-ness of a verilog wire through RTLIL	2020-04-27 09:44:24 -07:00
simplify.cc	Merge pull request #1851 from YosysHQ/claire/bitselwrite	2020-04-21 18:46:52 +02:00