yosys/techlibs/common
Eddie Hung d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Makefile.inc techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
abc9_model.v Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
adff2dff.v Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib Added cells.lib 2015-01-16 15:50:42 +01:00
cmp2lcu.v cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp 2020-04-03 14:28:22 -07:00
cmp2lut.v Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
gen_fine_ffs.py simcells.v: Generate the fine FF cell types by a python script. 2020-04-02 18:37:15 +02:00
mul2dsp.v Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v simcells.v: Generate the fine FF cell types by a python script. 2020-04-02 18:37:15 +02:00
simlib.v Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
synth.cc synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
techmap.v techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00