yosys/tests/sat
Eddie Hung 5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
..
.gitignore Added test cases for sat command 2014-02-04 13:43:34 +01:00
asserts.v Added test cases for sat command 2014-02-04 13:43:34 +01:00
asserts.ys Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
asserts_seq.v Added test cases for sat command 2014-02-04 13:43:34 +01:00
asserts_seq.ys Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
clk2fflogic.ys More rigorous test 2020-01-16 09:15:42 -08:00
counters-repeat.v support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
counters-repeat.ys support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
counters.v Added counters sat test case 2014-02-06 01:00:56 +01:00
counters.ys Added counters sat test case 2014-02-06 01:00:56 +01:00
expose_dff.v Added test cases for expose -evert-dff 2014-02-08 21:31:56 +01:00
expose_dff.ys Added test cases for expose -evert-dff 2014-02-08 21:31:56 +01:00
initval.v Wire with init on FF part, 1'bx on non-FF part 2019-08-24 15:05:44 -07:00
initval.ys Even more obvious testcase 2019-12-11 23:52:05 -08:00
run-test.sh Added test cases for sat command 2014-02-04 13:43:34 +01:00
share.v Added yet another resource sharing test case 2014-07-20 21:15:01 +02:00
share.ys Added yet another resource sharing test case 2014-07-20 21:15:01 +02:00
sizebits.sv Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
sizebits.ys Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
splice.v Added splice command 2014-02-07 20:30:56 +01:00
splice.ys Added splice command 2014-02-07 20:30:56 +01:00