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.gitignore
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Added first help messages for cell types
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2015-10-14 16:27:42 +02:00 |
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Makefile.inc
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abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
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2020-05-14 10:33:56 -07:00 |
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abc9_map.v
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abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
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2020-05-14 16:44:35 -07:00 |
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abc9_model.v
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abc9_ops/xaiger: further reducing Module::derive() calls by ...
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2020-05-14 10:33:57 -07:00 |
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abc9_unmap.v
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abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
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2020-05-29 17:17:40 -07:00 |
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adff2dff.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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cellhelp.py
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Progress on cell help messages
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2015-10-17 02:35:19 +02:00 |
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cells.lib
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Added cells.lib
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2015-01-16 15:50:42 +01:00 |
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cmp2lcu.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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cmp2lut.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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dff2ff.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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gate2lut.v
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Fix invalid verilog syntax
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2020-03-14 14:33:44 +01:00 |
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gen_fine_ffs.py
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Fix the truth table for $_SR_* cells.
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2020-04-15 17:17:48 +02:00 |
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mul2dsp.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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pmux2mux.v
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Added techlibs/common/pmux2mux.v
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2014-01-17 20:06:15 +01:00 |
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prep.cc
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Add "wreduce -keepdc", fixes #1016
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2019-05-20 15:36:13 +02:00 |
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simcells.v
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Fix the truth table for $_SR_* cells.
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2020-04-15 17:17:48 +02:00 |
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simlib.v
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Add flooring division operator
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2020-05-28 22:59:04 +02:00 |
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synth.cc
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synth: only techmap cmp2{lut,lcu} if -lut
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2020-04-03 14:28:22 -07:00 |
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techmap.v
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Add flooring division operator
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2020-05-28 22:59:04 +02:00 |
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