yosys/frontends/verilog
Clifford Wolf 375c4dddc1 Added read_verilog -icells option 2014-01-29 00:59:28 +01:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
const2ast.cc Fixed handling of unsized constants in verilog frontend 2014-01-24 15:05:24 +01:00
lexer.l Added Verilog parser support for asserts 2014-01-19 04:18:22 +01:00
parser.y Added Verilog parser support for asserts 2014-01-19 04:18:22 +01:00
preproc.cc Fixed parsing of verilog macros at end of line 2014-01-18 19:22:20 +01:00
verilog_frontend.cc Added read_verilog -icells option 2014-01-29 00:59:28 +01:00
verilog_frontend.h Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) 2013-11-22 12:46:02 +01:00