mirror of https://github.com/YosysHQ/yosys.git
e82e5f8b13
There's a mismatch between what `kernel/mem.cc` emits for memories with no read ports and what the internal RTLIL check expects. The point of dispute it whether some of the parameters relating to read ports have a zero-width value in this case. The `mem.cc` code says no, the internal checker says yes. Surveying the other `$mem_v2` parameters, and internal cell parameters in general, I am inclined to side with the `mem.cc` code. This breaks RTLIL compatibility but for an obscure edge case. |
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| .. | ||
| .gitignore | ||
| amber23_sram_byte_en.v | ||
| firrtl_938.v | ||
| implicit_en.v | ||
| issue00335.v | ||
| issue00710.v | ||
| no_implicit_en.v | ||
| nordports.ys | ||
| read_arst.v | ||
| read_two_mux.v | ||
| run-test.sh | ||
| shared_ports.v | ||
| simple_sram_byte_en.v | ||
| trans_addr_enable.v | ||
| trans_sdp.v | ||
| trans_sp.v | ||
| wide_all.v | ||
| wide_read_async.v | ||
| wide_read_mixed.v | ||
| wide_read_sync.v | ||
| wide_read_trans.v | ||
| wide_thru_priority.v | ||
| wide_write.v | ||