Commit Graph

12868 Commits

Author SHA1 Message Date
github-actions[bot] 88c849d112 Bump version 2023-06-04 00:19:27 +00:00
Claire Xenia Wolf d7f25165a5 Add ninitff line to aiger .aim files
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-06-03 14:38:22 +02:00
N. Engelhardt 0707b911c7 show: add -viewer none option 2023-06-01 11:00:07 +02:00
N. Engelhardt 4b986c9c65 fix wire color after BUF 2023-05-31 17:38:46 +02:00
Patrick Urban 2004a9ff4a gatemate: Add CC_FIFO_40K simulation model 2023-05-30 09:06:23 +02:00
Patrick Urban c244a7161b gatemate: Fix SDP read behavior 2023-05-30 09:05:43 +02:00
github-actions[bot] 43b807fe6f Bump version 2023-05-30 00:17:12 +00:00
Marcus Comstedt 1cd1e57e3c Fix use of non-POSIX test expressions in Makefile
POSIX test only allows "=" for string comparison.  Accepting "==" as
an alias is a bashism.  Even the bash manpage discourages its use.
2023-05-29 16:53:50 +02:00
Lofty fb7af093a8 intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
N. Engelhardt 26555a998d show -colorattr: extend colors to arrows when wires have attribute 2023-05-26 17:18:21 +02:00
github-actions[bot] 8596c5ce49 Bump version 2023-05-26 00:15:52 +00:00
Krystine Sherwin 3aee765793
Initial version of memory mapping doc 2023-05-26 09:36:01 +12:00
Lofty cac1bc6fbe intel_alm: enable M10K initialisation 2023-05-25 18:56:34 +01:00
Eddie Hung ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Eddie Hung 862631d657 Add ABC9 DSP cascade test 2023-05-25 18:42:08 +01:00
Lofty 00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
2023-05-25 12:48:02 +02:00
Jannis Harder 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization 2023-05-25 12:46:16 +02:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
github-actions[bot] 57c9eb70fe Bump version 2023-05-24 00:15:32 +00:00
Miodrag Milanović 5e36effe3c
Merge pull request #3777 from YosysHQ/micko/vhdl_verific
Fix importing parametrized VHDL entity
2023-05-23 11:44:49 +02:00
Miodrag Milanovic ecd289c100 Fix importing parametrized VHDL entity 2023-05-23 08:25:08 +02:00
Jannis Harder 4f3d1be96a
Merge pull request #3767 from YosysHQ/krys/yw_fix
Assign wires an smtoffset
2023-05-22 16:10:55 +02:00
Jannis Harder 5fb1223861
Merge pull request #3733 from AdamHillier/aiger-inputs
Add outputs before inputs to the sigmap in the AIGER backend.
2023-05-22 16:09:15 +02:00
N. Engelhardt 890849447f
Merge pull request #3716 from antmicro/kr/brackets 2023-05-22 16:06:38 +02:00
github-actions[bot] cdeef5481c Bump version 2023-05-22 00:16:53 +00:00
Krystine Sherwin 18b44a1e84
yosys-witness: add append option to yw2yw
Can now append a user defined number of steps to input traces when joining.
If the number of steps is +ve, inputs are all set to 0.
If -ve then steps are skipped.
If all of steps are skipped (including init step) then the input trace will not be copied.
If more than one input trace is provided, the append option will need to be provided the same number of times as there are input traces.
2023-05-22 11:44:19 +12:00
Krystine Sherwin 8c9a0b51d4
yosys-witness concat yw trace files
Intended for use with SCY to combine sequential cover traces.
Arbitrary number of inputs, will load all and attempt to join them.  Each trace will be replayed one after the other, in the same order as the files are provided.
Mismatch in init_only fields seems to work fine, with values in subsequent traces being assigned in the initial only if they weren't previously defined.
Uncertain if a mismatch in non init_only fields will cause problems.
Fixes WitnessSig.__eq__().
Adds helper functions to WitnessValues and ReadWitness classes.
2023-05-22 10:13:17 +12:00
CORRADI Quentin e7156c644d Standard compliance for tests/verilog/block_labels.ys
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
2023-05-21 16:38:14 -04:00
Jannis Harder ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
2023-05-18 16:50:11 +02:00
Jannis Harder e6f3914800 smt2: Use smt bv offset for `$any*`'s smtoffset
While not setting the smtoffset here was clearly a bug, I think using
`chunk.offset` only worked incidentally. The `smtoffset` is an offset
into the `smtname, smtid` pair (here `"", idcounter`) which corresponds
to the smt bitvector `stringf("%s#%d", get_id(module), idcounter)` which
contains all the chunks this loop is iterating over.

Thus using an incrementing `smtoffset` (like the `$ff`/`$dff` case above
already does) should be the correct fix.
2023-05-18 11:58:09 +02:00
github-actions[bot] 147cceb516 Bump version 2023-05-18 00:15:34 +00:00
Krystine Sherwin 52ad7a47f3
Assign wires an smtoffset
Wires weren't being assigned an smtoffset value so when generating a yosys witness trace it would also use an offset of 0.
Not sure if this has any other effects, but it fixes the bug I was having.
@jix could you take a look at this?
2023-05-18 10:37:55 +12:00
Miodrag Milanovic c2285b3460 fix file rights 2023-05-17 13:39:57 +02:00
Miodrag Milanović 07e76fcaca
Merge pull request #3751 from RTLWorks/main/issue2525
[YOSYS-2525] fix read_liberty newline handling #2525
2023-05-17 13:33:34 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை) 693c609eec
Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
Muthu Annamalai 665e0f6131 remove new line per maintainer request 2023-05-17 04:20:13 +00:00
Miodrag Milanović acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
2023-05-15 16:34:35 +02:00
Kamil Rakoczy 6b3e6d96a3 Fix missing brackets around else
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2023-05-10 08:09:11 +02:00
github-actions[bot] d82bae32be Bump version 2023-05-10 00:15:03 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை) c855502bd5
Update passes/techmap/libparse.cc
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
2023-05-09 06:40:21 -07:00
Miodrag Milanović 7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script
gowin: Add all the primitives.
2023-05-09 11:13:51 +02:00
Miodrag Milanović 5c7cc6ff06
Merge pull request #3745 from rfuest/gowin_alu
gowin: Fix X output of $alu techmap
2023-05-09 11:12:50 +02:00
Miodrag Milanović 226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff
Updated the `plugin` command to better handle paths
2023-05-09 08:46:02 +02:00
Miodrag Milanovic f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic 9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
github-actions[bot] 0469405abf Bump version 2023-05-09 00:15:34 +00:00
N. Engelhardt 266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt 0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
N. Engelhardt ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00