yosys

Commit Graph

Author	SHA1	Message	Date
Miodrag Milanovic	d8adbff72f	Handle possible non-memory indexed data	2022-05-06 08:05:23 +02:00
Miodrag Milanovic	8b3657454b	map memory location to wire value, if memory is converted to FFs	2022-05-04 13:08:16 +02:00
Miodrag Milanovic	ad48639cdd	Start restoring memory state from VCD/FST	2022-05-04 10:41:04 +02:00
Miodrag Milanovic	9c7deabf94	Ignore change on last edge	2022-04-22 15:24:02 +02:00
Miodrag Milanovic	2e47b61cc6	Proper scope naming from FST	2022-03-30 15:55:15 +02:00
Miodrag Milanovic	55eed8df57	More verbose warnings	2022-03-18 14:47:35 +01:00
Miodrag Milanovic	1f3423cd7d	Recognize registers and set initial state for them in tb	2022-03-16 14:35:39 +01:00
Miodrag Milanovic	8be09b5b24	VCD reader support by using external tool	2022-02-28 09:09:07 +01:00
Miodrag Milanovic	fca168797e	Fix for last clock edge data	2022-02-25 16:15:32 +01:00
Miodrag Milanovic	5f918803de	Changed error message	2022-02-18 15:06:49 +01:00
Miodrag Milanovic	fb22d7cdc4	Add support for various ff/latch cells simulation	2022-02-16 13:27:59 +01:00
Miodrag Milanovic	c0a156bcb4	Error detection for co-simulation	2022-02-04 11:11:36 +01:00
Miodrag Milanovic	6db23de7b1	bug fix and cleanups	2022-02-04 10:01:06 +01:00
Miodrag Milanovic	26de52fa09	Cleanup	2022-01-31 12:00:15 +01:00
Miodrag Milanovic	543feb75cb	Display simulation time data	2022-01-31 10:52:47 +01:00
Miodrag Milanovic	cb12b7c4d8	ignore not found private signals	2022-01-28 14:20:16 +01:00
Miodrag Milanovic	f0f3c81c56	preserve VCD mangled names	2022-01-28 14:10:39 +01:00
Miodrag Milanovic	72acce0c82	detect edges even when x	2022-01-28 13:53:27 +01:00
Miodrag Milanovic	a8d03df173	cleanup	2022-01-28 12:54:16 +01:00
Miodrag Milanovic	4f75a2ca1b	Do actual compare	2022-01-28 12:50:41 +01:00
Miodrag Milanovic	3e35de2be1	Add more options and time handling	2022-01-28 10:18:02 +01:00
Miodrag Milanovic	8a02616465	Add fstdata helper class	2022-01-26 10:23:38 +01:00

22 Commits