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5209 Commits

Author SHA1 Message Date
Clifford Wolf f01a61f093 Rename implicit_ports.sv test to implicit_ports.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 13:12:25 +02:00
Clifford Wolf 211d85cfcc Fixes and cleanups in AST_TECALL handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 12:41:09 +02:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf 169de05f3b Merge branch 'tux3-implicit_named_connection' 2019-06-07 11:53:46 +02:00
Clifford Wolf 7116621d22
Merge pull request #1076 from thasti/centos7-build-fix 
Fix pyosys-build on CentOS7
 2019-06-07 11:48:33 +02:00
Clifford Wolf a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
Stefan Biereigel d018e02614 remove boost/log/exceptions.hpp from wrapper generator 2019-06-07 09:47:33 +02:00
tux3 88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Clifford Wolf b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn 
Added support for parsing attributes on port connections.
 2019-06-06 12:34:05 +02:00
David Shah 30cedaca10
Merge pull request #1073 from whitequark/ecp5-diamond-iob 
ECP5: implement most Diamond I/O buffer primitives
 2019-06-06 11:22:49 +01:00
whitequark f3a26730b6 ECP5: implement all Diamond I/O buffer primitives. 2019-06-06 10:18:33 +00:00
Clifford Wolf e4e1cd6930
Merge pull request #1071 from YosysHQ/eddie/fix_1070 
Fix typo in opt_rmdff causing register to be incorrectly removed
 2019-06-06 06:50:12 +02:00
Clifford Wolf 50e2dce5e7
Merge pull request #1072 from YosysHQ/eddie/fix_1069 
Error out if no top module given before 'sim'
 2019-06-06 06:49:07 +02:00
Eddie Hung fd8ef128bf Missing doc for -tech xilinx in shregmap 2019-06-05 14:21:44 -07:00
Eddie Hung dd134914cc Error out if no top module given before 'sim' 2019-06-05 14:16:24 -07:00
Eddie Hung feb2ddb52b Fix typo in opt_rmdff 2019-06-05 14:08:14 -07:00
Eddie Hung a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065 
Suppress driver-driver conflict warning for unknown cell types
 2019-06-05 09:59:05 -07:00
Maciej Kurc 03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Clifford Wolf f15b5e6309
Merge pull request #1066 from YosysHQ/clifford/fix1056 
Remove yosys_banner() from python wrapper init
 2019-06-05 10:37:39 +02:00
Clifford Wolf b33176dafb Major rewrite of wire selection in setundef -init 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 10:26:48 +02:00
Clifford Wolf 6cc60ffd67 Indent fix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:53:06 +02:00
Clifford Wolf 00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix 
initialize more registers in setundef -init
 2019-06-05 09:50:15 +02:00
Clifford Wolf 4190d7c094 Fix typo in fmcombine log message, fixes #1063 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:26:44 +02:00
Clifford Wolf 8a6f9977f6 Suppress driver-driver conflict warning for unknown cell types, fixes #1065 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:14:12 +02:00
Clifford Wolf dd3c333c0a Remove yosys_banner() from python wrapper init, fixes #1056 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 08:57:33 +02:00
Clifford Wolf 1332051f33
Merge pull request #1062 from tux3/patch-1 
README.md: Missing formatting for <tag>
 2019-06-04 14:37:10 +02:00
Tux3 c66d644b66
README.md: Missing formatting for <tag> 2019-06-04 10:45:41 +02:00
Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Eddie Hung 1217e47e83
Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map 
Execute techmap and arith_map simultaneously
 2019-06-03 20:23:37 -07:00
Eddie Hung 02973474df Remove extra newline 2019-06-03 20:04:47 -07:00
Eddie Hung 0ad50332d9 Execute techmap and arith_map simultaneously 2019-06-03 19:36:09 -07:00
Maciej Kurc 5739cf5265 Added tests for attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-03 09:25:20 +02:00
Clifford Wolf 36120fcc30 Only support Symbiotic EDA flavored Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-02 10:14:50 +02:00
Maciej Kurc a6cadf6318 Added support for parsing attributes on port connections. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-31 14:58:43 +02:00
Clifford Wolf 90ec2cda42 Fix "tee" handling of log_streams 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-31 09:28:51 +02:00
Clifford Wolf 2faa1d0e80 Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-30 10:04:26 +02:00
Clifford Wolf 0df8a3b461
Merge pull request #1057 from mmicko/fix_478 
Aded one more load of .conf to support change of prefix
 2019-05-30 09:58:51 +02:00
Miodrag Milanovic 14bd40cd3d Aded one more load of .conf to support change of prefix 2019-05-29 18:57:03 +02:00
Clifford Wolf 349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047 
Do not use shiftmul peepopt pattern when mul result is truncated
 2019-05-28 19:02:26 +02:00
Clifford Wolf 8e647901ef
Merge pull request #1050 from YosysHQ/clifford/wandwor 
Refactored wand/wor support
 2019-05-28 17:42:16 +02:00
Clifford Wolf cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 17:17:56 +02:00
Clifford Wolf 49d641d97f
Merge pull request #1048 from mmicko/fix_enable_pyosys 
Moved pyosys block in Makefile
 2019-05-28 16:52:40 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Clifford Wolf e3ebac44df Add actual wandwor test that is part of "make test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:42:50 +02:00
Clifford Wolf eaae0adf57 Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor 2019-05-28 15:45:15 +02:00
Miodrag Milanovic 040b06cb37 Remove info line in 2nd load of conf file 2019-05-28 15:43:27 +02:00
Miodrag Milanovic 1575d962fa Moved pyosys block in Makefile 2019-05-28 14:53:07 +02:00
Clifford Wolf 2a11c48782
Merge pull request #1045 from mmicko/afl-gcc-target 
afl-fuzzer compile config
 2019-05-28 14:00:28 +02:00
Miodrag Milanovic 1bbcd277fb make config-afl-gcc to help creating conf file 2019-05-27 20:43:10 +02:00