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7626 Commits

Author SHA1 Message Date
Eddie Hung f2f19df2d4 Add -select option to aigmap 2019-09-30 15:26:29 -07:00
Eddie Hung eecfdda614 Cleanup 2019-09-30 15:24:03 -07:00
Eddie Hung e0aa772663 Add comment 2019-09-30 15:19:02 -07:00
Eddie Hung d963e8c2c6 Fix typo 2019-09-30 15:18:40 -07:00
Eddie Hung 0a1af434e8 Fix for svinterfaces 2019-09-30 14:52:04 -07:00
Eddie Hung 08b55a20e3 module->derive() to be lazy and not touch ast if already derived 2019-09-30 14:11:01 -07:00
Eddie Hung 74678227c7 Use a cell_cache to instantiate once rather than opt_merge call 2019-09-30 13:21:07 -07:00
Eddie Hung a6994c5f16 scc call on active module module only, plus cleanup 2019-09-30 12:57:19 -07:00
Eddie Hung bd8356799a Use derived module 2019-09-30 12:34:28 -07:00
Eddie Hung 8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung a274b7cc86 Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
whitequark 5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00
Eddie Hung ed47bd78e1
Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors 
Generate Python wrappers for inline constructors
 2019-09-30 10:31:57 -07:00
whitequark 99a7f39084 rpc: new frontend. 
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
 2019-09-30 15:53:11 +00:00
whitequark 8f2bdff7b9 libs: import json11. 
This commit imports the code from upstream commit
dropbox/json11@8ccf1f0c5e.
 2019-09-30 15:53:11 +00:00
Miodrag Milanović 0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Clifford Wolf 7ed13297b1 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 17:08:38 +02:00
Clifford Wolf 0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync 
equiv_opt to call async2sync when not -multiclock like SymbiYosys
 2019-09-30 17:04:21 +02:00
Clifford Wolf dd67e8ce73
Merge pull request #1417 from YosysHQ/clifford/fixasync2sync 
Fix $dlatch handling in async2sync
 2019-09-30 17:04:03 +02:00
Clifford Wolf 10e57f3880 Fix $dlatch handling in async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 14:58:23 +02:00
Eddie Hung 6216e45eda Add latch test modified from #1363 2019-09-30 12:52:43 +02:00
Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung f6203e6bd6 Missing endmodule 2019-09-29 21:55:53 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map 
Avoid work in replace() if rules empty.
 2019-09-29 19:35:23 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 18ebb86edb FDCE_1 does not have IS_CLR_INVERTED 2019-09-29 11:25:34 -07:00
Eddie Hung 5a4011e8c9 Fix "scc" call inside abc9 to consider all wires 2019-09-29 09:58:00 -07:00
Eddie Hung f3e150d9a5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 09:21:51 -07:00
Miodrag Milanovic 9e55b234b4 Fix reading aig files on windows 2019-09-29 15:40:37 +02:00
Miodrag Milanovic 3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Miodrag Milanović ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out 
Support binary files for backends, fixes #1407
 2019-09-29 10:37:34 +02:00
Clifford Wolf 178c67ea22
Merge pull request #1411 from aman-goel/YosysHQ-master 
Corrects BTOR2 backend
 2019-09-29 10:36:25 +02:00
Henner Zeller 8c2b4f0a50 Avoid work in replace() if rules empty. 
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2019-09-29 00:17:40 -07:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Miodrag Milanovic 0c380f0855 Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
Miodrag Milanovic d0493925ec Support binary files for backends, fixes #1407 2019-09-28 09:36:18 +02:00
Eddie Hung c372e7baf9 Fix box name 2019-09-27 18:49:45 -07:00
Eddie Hung cfa6dd61ef Use abc_mergeability attr for "r" extension 2019-09-27 18:41:43 -07:00
Eddie Hung 313d2478e9 Split ABC9 based on clocking only, add "abc_mergeability" attr for en 2019-09-27 18:41:04 -07:00
Eddie Hung dc154c39a8 Fix infinite recursion 2019-09-27 17:45:49 -07:00
Eddie Hung fe722b737c Add -select option to aigmap 2019-09-27 17:44:01 -07:00
Eddie Hung 11cb5fab00 Fix typo 2019-09-27 17:00:19 -07:00
Eddie Hung 8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung a39505e329 equiv_opt to call async2sync when not -multiclock like SymbiYosys 2019-09-27 12:59:10 -07:00
Eddie Hung aebbfffd71 Ooops AREG and BREG to default to -1 2019-09-27 11:57:53 -07:00
Aman Goel 5eebfabe42 Corrects btor2 backend 2019-09-27 12:40:17 -04:00