riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,556 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

7556 Commits

Author SHA1 Message Date
Miodrag Milanović da347b9f7e
Merge pull request #1426 from YosysHQ/mmicko/fix_environ 
Define environ, fixes #1424
 2019-10-01 19:50:37 +02:00
Miodrag Milanovic c026579c20 Define environ, fixes #1424 2019-10-01 18:45:07 +02:00
Eddie Hung d963e8c2c6 Fix typo 2019-09-30 15:18:40 -07:00
Eddie Hung a274b7cc86 Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
whitequark 5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00
Eddie Hung ed47bd78e1
Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors 
Generate Python wrappers for inline constructors
 2019-09-30 10:31:57 -07:00
whitequark 99a7f39084 rpc: new frontend. 
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
 2019-09-30 15:53:11 +00:00
whitequark 8f2bdff7b9 libs: import json11. 
This commit imports the code from upstream commit
dropbox/json11@8ccf1f0c5e.
 2019-09-30 15:53:11 +00:00
Miodrag Milanović 0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Clifford Wolf 7ed13297b1 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 17:08:38 +02:00
Clifford Wolf 0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync 
equiv_opt to call async2sync when not -multiclock like SymbiYosys
 2019-09-30 17:04:21 +02:00
Clifford Wolf dd67e8ce73
Merge pull request #1417 from YosysHQ/clifford/fixasync2sync 
Fix $dlatch handling in async2sync
 2019-09-30 17:04:03 +02:00
Clifford Wolf 10e57f3880 Fix $dlatch handling in async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 14:58:23 +02:00
Eddie Hung 6216e45eda Add latch test modified from #1363 2019-09-30 12:52:43 +02:00
Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map 
Avoid work in replace() if rules empty.
 2019-09-29 19:35:23 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Miodrag Milanovic 9e55b234b4 Fix reading aig files on windows 2019-09-29 15:40:37 +02:00
Miodrag Milanovic 3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Miodrag Milanović ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out 
Support binary files for backends, fixes #1407
 2019-09-29 10:37:34 +02:00
Clifford Wolf 178c67ea22
Merge pull request #1411 from aman-goel/YosysHQ-master 
Corrects BTOR2 backend
 2019-09-29 10:36:25 +02:00
Henner Zeller 8c2b4f0a50 Avoid work in replace() if rules empty. 
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2019-09-29 00:17:40 -07:00
Miodrag Milanovic 0c380f0855 Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
Miodrag Milanovic d0493925ec Support binary files for backends, fixes #1407 2019-09-28 09:36:18 +02:00
Eddie Hung c372e7baf9 Fix box name 2019-09-27 18:49:45 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung a39505e329 equiv_opt to call async2sync when not -multiclock like SymbiYosys 2019-09-27 12:59:10 -07:00
Eddie Hung aebbfffd71 Ooops AREG and BREG to default to -1 2019-09-27 11:57:53 -07:00
Aman Goel 5eebfabe42 Corrects btor2 backend 2019-09-27 12:40:17 -04:00
Marcin Kościelnicki fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
 2019-09-27 18:34:12 +02:00
Aman Goel cb0dc6e68b
Merge pull request #7 from YosysHQ/master 
Syncing with official repo
 2019-09-27 12:30:27 -04:00
Miodrag Milanović 4b15cf5f76
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt_difference 
Change order of parameters, to work on other OS
 2019-09-27 17:37:55 +02:00
Miodrag Milanovic 7f0eec8270 Change order of parameters, to work on other os 2019-09-27 11:31:55 +02:00
Clifford Wolf 7bde555481
Merge pull request #1404 from YosysHQ/fix_gzip_macos 
Make read/write gzip files on macos works, fixes #1357
 2019-09-27 09:57:28 +02:00
Eddie Hung 26657037b8 Update doc with max cascade chain of 20 2019-09-26 14:31:02 -07:00
Eddie Hung 5b9deef10d Do not always zero out C (e.g. during cascade breaks) 2019-09-26 13:59:05 -07:00
Eddie Hung 95f0dd57df Update doc 2019-09-26 13:44:41 -07:00
Eddie Hung 58f31096ab Zero out ports 2019-09-26 13:40:38 -07:00
Eddie Hung af59856ba1 xilinx_dsp_cascade to also cascade AREG and BREG 2019-09-26 13:29:18 -07:00
Eddie Hung 832216dab0 Try recursive pmgen for P cascade 2019-09-26 12:09:57 -07:00
Eddie Hung 143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung 84825f9378 Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once 2019-09-26 10:45:14 -07:00
Miodrag Milanovic 435300f930 Make read/write gzip files on macos works, fixes #1357 2019-09-26 19:35:12 +02:00
Eddie Hung 033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung bd8661e024 CREG to check for \keep 2019-09-26 10:32:01 -07:00
Eddie Hung c0bb1d22e8 Remove newline 2019-09-26 10:31:55 -07:00
Eddie Hung 781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00