Commit Graph

4277 Commits

Author SHA1 Message Date
Clifford Wolf 23bb77867f Minor style fixes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 20:02:39 +01:00
Clifford Wolf 2d73e1b60a
Merge pull request #748 from makaimann/add-btor-ops
Add btor ops for $mul, $div, $mod and $concat
2018-12-18 19:59:29 +01:00
Clifford Wolf eddf075d93
Merge pull request #751 from daveshah1/fix_589
memory_dff: Fix typo when checking init value
2018-12-18 19:55:42 +01:00
David Shah 2b16d4ed3d memory_dff: Fix typo when checking init value
Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-18 17:40:01 +00:00
Clifford Wolf fdf7c42181 Fix segfault in AST simplify
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 17:49:38 +01:00
Icenowy Zheng 4bf8ac728c anlogic: set the init value of DFFs
As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.

Support for set the init values of Anlogic DFFs.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:16:37 +08:00
Icenowy Zheng 256fb8c95c Add "dffinit -noreinit" parameter
Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.

Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:10:40 +08:00
Clifford Wolf 3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 16:01:22 +01:00
Icenowy Zheng fec8b3c81f Add "dffinit -strinit high low"
On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".

Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 15:37:43 +08:00
Icenowy Zheng 7854d5ba21 anlogic: fix dbits of Anlogic Eagle DRAM16X4
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.

Fix the dbits number in the RAM configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 14:38:44 +08:00
makaimann abf5930a33 Add btor ops for $mul, $div, $mod and $concat 2018-12-17 10:45:17 -08:00
Clifford Wolf 847fd36077
Merge pull request #746 from Icenowy/anlogic-dram
Support for DRAM inferring on Anlogic FPGAs
2018-12-17 17:16:10 +01:00
Clifford Wolf 3b4290a1b8
Merge pull request #742 from whitequark/changelog
Update CHANGELOG to mention my improvements
2018-12-17 16:35:56 +01:00
Clifford Wolf 97b49d6e45
Merge pull request #741 from whitequark/ilang_slice_sigspec
read_ilang: allow slicing all sigspecs, not just wires
2018-12-17 16:29:25 +01:00
Clifford Wolf ce701fd334
Merge pull request #744 from whitequark/write_verilog_$shift
write_verilog: handle the $shift cell
2018-12-17 16:26:57 +01:00
Icenowy Zheng d53a2bd1d3 anlogic: add support for Eagle Distributed RAM
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Icenowy Zheng 634d7d1c14 Revert "Leave only real black box cells"
This reverts commit 43030db5ff.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Clifford Wolf dc6e63d8cd
Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:56 +01:00
Clifford Wolf 2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress" 2018-12-16 21:27:31 +01:00
whitequark ca866d384e write_verilog: handle the $shift cell.
The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule
2018-12-16 18:46:32 +00:00
whitequark 9f5c7017ff Update CHANGELOG. 2018-12-16 18:26:00 +00:00
whitequark 4effb38e6d read_ilang: allow slicing sigspecs. 2018-12-16 17:53:26 +00:00
Clifford Wolf ddff75b60a
Merge pull request #736 from whitequark/select_assert_list
select: print selection if a -assert-* flag causes an error
2018-12-16 16:45:49 +01:00
whitequark f6412d7109 select: print selection if a -assert-* flag causes an error. 2018-12-16 15:44:29 +00:00
Clifford Wolf 5fa5dbbdda Rename "fine:" label to "map:" in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 16:36:19 +01:00
Clifford Wolf 4c5173045b
Merge pull request #704 from webhat/feature/fix-awk
Using awk rather than gawk
2018-12-16 16:31:37 +01:00
whitequark fccaa25ec1 write_verilog: add a missing newline. 2018-12-16 15:22:34 +00:00
Clifford Wolf ac27a5a737
Merge pull request #738 from smunaut/issue_737
verilog_parser: Properly handle recursion when processing attributes
2018-12-16 16:05:14 +01:00
Clifford Wolf 0d9c850a07
Merge pull request #735 from daveshah1/trifixes
deminout fixes
2018-12-16 16:02:21 +01:00
Clifford Wolf 1e1452c7ff
Merge pull request #739 from whitequark/patch-1
Add .editorconfig file
2018-12-16 16:01:13 +01:00
whitequark 8f359cf1ff
Add .editorconfig file.
See https://editorconfig.org/ for details.
2018-12-16 14:57:43 +00:00
Clifford Wolf f53e19cc71 Fix equiv_opt indenting
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 15:57:28 +01:00
Clifford Wolf 2a681909df
Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
Clifford Wolf ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
Clifford Wolf f481ad4d44
Merge pull request #729 from whitequark/write_verilog_initial
write_verilog: correctly map RTLIL `sync init`
2018-12-16 15:50:16 +01:00
Clifford Wolf 0c69f1d777
Merge pull request #725 from olofk/ram4k-init
Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
Clifford Wolf a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
Clifford Wolf 9522eee02f
Merge pull request #723 from whitequark/synth_ice40_map_gates
synth_ice40: split `map_gates` off `fine`
2018-12-16 15:30:08 +01:00
Clifford Wolf 19ca4e2ac3
Merge pull request #722 from whitequark/rename_src
rename: add -src, for inferring names from source locations
2018-12-16 15:28:29 +01:00
Clifford Wolf 556341a77f
Merge pull request #720 from whitequark/master
lut2mux: handle 1-bit INIT constant in $lut cells
2018-12-16 15:27:23 +01:00
Sylvain Munaut 58fb2ac818 verilog_parser: Properly handle recursion when processing attributes
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
David Shah 4c59447168 deminout: Consider $tribuf cells
Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah d3fe9465f3 deminout: Don't demote constant-driven inouts to inputs
Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
Graham Edgecombe 4fef9689ab memory_bram: Fix initdata bit order after shuffling
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.

This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).

This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
2018-12-11 21:02:49 +00:00
Clifford Wolf 0b9bb852c6 Add yosys-smtbmc support for btor witness
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-10 03:43:07 +01:00
Sylvain Munaut add6ab9b2a ice40: Honor the "dont_touch" attribute in FFSSR pass
This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
Clifford Wolf 47a5dfdaa4 Add "yosys-smtbmc --btorwit" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:59:27 +01:00
Clifford Wolf ed3c57fad3 Fix btor init value handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:21:31 +01:00
whitequark 7fe770a441 write_verilog: correctly map RTLIL `sync init`. 2018-12-07 18:55:08 +00:00