d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap
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flowmap: new techmap pass
2019-01-03 17:03:18 +01:00
07af772a72
flowmap: new techmap pass.
2019-01-03 14:28:19 +00:00
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp
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opt_expr: refactor and improve simplification of comparisons
2019-01-02 17:34:04 +01:00
bf8db55ef3
opt_expr: improve simplification of comparisons with large constants.
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The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.
However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.
This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init
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anlogic: implement DRAM initialization
2019-01-02 16:28:18 +01:00
b236faffa1
Merge branch 'master' of github.com:YosysHQ/yosys
2019-01-02 15:53:50 +01:00
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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opt_lut: elimination fixes
2019-01-02 15:45:29 +01:00
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
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synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut
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cmp2lut: new techmap pass
2019-01-02 15:43:10 +01:00
1eb101a38a
Improve VerificImporter support for writes to asymmetric memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:33:43 +01:00
50b09de033
Fix VerificImporter asymmetric memories error message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:05:23 +01:00
16bb823db8
Merge pull request #769 from whitequark/typos
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Fix typographical and grammatical errors and inconsistencies
2019-01-02 14:47:18 +01:00
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
c55dfb8369
opt_lut: reflect changes in sigmap.
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Otherwise, some LUTs will be missed during elimination.
2019-01-02 10:21:58 +00:00
06143ab33f
opt_lut: use a worklist, and revisit cells affected by elimination.
2019-01-02 09:36:32 +00:00
f7363ac508
opt_lut: count eliminated cells, and set opt.did_something for them.
2019-01-02 09:14:43 +00:00
17b2831356
synth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 08:25:55 +00:00
18174202a9
synth: add k-LUT mode.
2019-01-02 08:25:03 +00:00
fdff32dd73
synth: improve script documentation. NFC.
2019-01-02 08:05:44 +00:00
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
4fd458290c
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
2019-01-02 05:11:29 +00:00
9e9846a6ea
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
2019-01-02 03:01:25 +00:00
8e53d2e0bf
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
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Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
2019-01-02 02:45:49 +00:00
4b9f619349
Merge pull request #768 from whitequark/opt_lut_elim
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opt_lut: eliminate LUTs evaluating to constants or inputs
2019-01-01 11:13:48 +01:00
42c356c49c
opt_lut: eliminate LUTs evaluating to constants or inputs.
2018-12-31 23:55:40 +00:00
0a840dd883
Fix handling of (* keep *) wires in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-31 16:37:40 +01:00
e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches
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anlogic: add latch cells
2018-12-31 15:52:01 +01:00
ebe9351f82
Fix 7 instances of add_share_file to add_gen_share_file
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in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
2018-12-29 12:53:12 +01:00
99706b3bf4
Squelch a little more trailing whitespace
2018-12-29 12:46:54 +01:00
1b36944299
anlogic: add latch cells
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Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-25 22:47:46 +08:00
245724a504
Merge pull request #761 from whitequark/proc_clean_partial
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proc_clean: remove any empty cases, if possible to do safely
2018-12-23 16:16:06 +01:00
6dad191377
Add "read_ilang -[no]overwrite"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-23 15:45:09 +01:00
d938ce7ab6
Merge branch 'master' of github.com:YosysHQ/yosys
2018-12-23 15:44:19 +01:00
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
e5eb3d2c8a
Merge pull request #757 from whitequark/manual_mem
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manual: document $meminit cell and memory_* passes
2018-12-22 20:12:18 +01:00
b784440857
proc_clean: remove any empty cases at the end of the switch.
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Previously, only completely empty switches were removed.
2018-12-22 09:04:46 +00:00
182d84ad54
manual: make description of $meminit ports match reality.
2018-12-21 23:04:31 +00:00
ee8a7589e0
Merge pull request #758 from whitequark/tcl_script_args
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tcl: add support for passing arguments to scripts
2018-12-21 17:56:43 +01:00
29a82acb2e
Merge pull request #759 from whitequark/memory_collect_init_x
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memory_collect: do not truncate 'x from \INIT
2018-12-21 17:39:52 +01:00
0c318e7db5
memory_collect: do not truncate 'x from \INIT.
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The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
2018-12-21 02:01:27 +00:00
c04908c997
manual: fix typos.
2018-12-20 07:59:40 +00:00
2ca237e086
tcl: add support for passing arguments to scripts.
2018-12-20 07:32:24 +00:00
a9ff81dd82
manual: document $meminit cell and memory_* passes.
2018-12-20 04:54:31 +00:00
90d00182cf
anlogic: implement DRAM initialization
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As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-20 07:56:15 +08:00
93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost
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Anlogic: let LUT5/6 have more cost than LUT4-
2018-12-19 19:52:31 +01:00
c98d44ac12
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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anlogic: fix Makefile.inc
2018-12-19 19:51:10 +01:00
4d84a456dc
Merge pull request #749 from Icenowy/anlogic-dram-fix
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anlogic: fix dbits of Anlogic Eagle DRAM16X4
2018-12-19 19:48:54 +01:00
3993ba71f7
anlogic: fix Makefile.inc
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During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.
Fix this issue.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 10:23:58 +08:00
c9513c695a
Anlogic: let LUT5/6 have more cost than LUT4-
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According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 09:36:53 +08:00
Clifford Wolf
whitequark
Larry Doolittle
Icenowy Zheng