Clifford Wolf
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d9641621d9
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Add "verific -import -n" and "verific -import -nosva"
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2017-07-27 11:54:45 +02:00 |
Clifford Wolf
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b24f737759
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
Clifford Wolf
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90d8329f64
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Improve Verific SVA import: negedge and $past
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2017-07-27 11:40:07 +02:00 |
Clifford Wolf
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147ff96ba3
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Improve Verific SVA importer
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2017-07-27 10:39:39 +02:00 |
Clifford Wolf
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649bb9374f
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Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
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2017-07-26 18:28:55 +02:00 |
Clifford Wolf
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530040ba6f
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Improve Verific bindings (mostly related to SVA)
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2017-07-26 18:00:01 +02:00 |
Clifford Wolf
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abd3b4e8e7
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Improve "help verific" message
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2017-07-25 15:13:22 +02:00 |
Clifford Wolf
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6dbe1d4c92
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Add "verific -extnets"
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2017-07-25 14:53:11 +02:00 |
Clifford Wolf
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493fedbaf9
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Add "using std::get" to yosys.h
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2017-07-25 14:52:34 +02:00 |
Clifford Wolf
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c97c92e4ec
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Improve "verific -all" handling
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2017-07-25 13:33:25 +02:00 |
Clifford Wolf
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41be530c4e
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Add "verific -import -d <dump_file"
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2017-07-24 13:57:16 +02:00 |
Clifford Wolf
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92d3aad670
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Add "verific -import -flatten" and "verific -import -v"
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2017-07-24 11:29:06 +02:00 |
Clifford Wolf
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84f15260b5
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Add more SVA test cases for future Verific work
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2017-07-22 16:35:46 +02:00 |
Clifford Wolf
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5be535517c
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Add "verific -import -k"
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2017-07-22 16:16:44 +02:00 |
Clifford Wolf
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b6bd12fade
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Add error for cell output ports that are connected to constants
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2017-07-22 15:08:30 +02:00 |
Clifford Wolf
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024ba310ec
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Add some simple SVA test cases for future Verific work
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2017-07-22 12:31:08 +02:00 |
Clifford Wolf
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2785aaffeb
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Improve docs for verific bindings, add simply sby example
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2017-07-22 11:58:51 +02:00 |
Clifford Wolf
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b3bc7068d1
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Fix handling of empty cell port assignments (i.e. ignore them)
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2017-07-21 19:32:31 +02:00 |
Clifford Wolf
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36cf18ac4c
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Fix "read_blif -wideports" handling of cells with wide ports
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2017-07-21 16:21:12 +02:00 |
Clifford Wolf
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26766da343
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Add a paragraph about pre-defined macros to read_verilog help message
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2017-07-21 14:34:53 +02:00 |
Clifford Wolf
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3a8f6f0f51
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Add verilator support to testbenches generated by yosys-smtbmc
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2017-07-21 14:33:29 +02:00 |
Clifford Wolf
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c251e3a576
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Change intptr_t to uintptr_t in hashlib.h
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2017-07-18 17:38:19 +02:00 |
Clifford Wolf
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dbb2f755c1
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Merge pull request #363 from rqou/master
Miscellaneous build tweaks
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2017-07-18 15:21:12 +02:00 |
Robert Ou
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85d667ca08
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makefile: Add the option to use libtermcap
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2017-07-17 14:21:59 -07:00 |
Robert Ou
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f0741698fa
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Fix build warnings for win64
Win64 has a 32-bit long. Use intptr_t to work on any data model.
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2017-07-17 12:36:43 -07:00 |
Clifford Wolf
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c00d8a5b73
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Add $alu to list of supported cells for "stat -width"
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2017-07-14 11:32:49 +02:00 |
Clifford Wolf
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10c7709e68
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Generate FSM-style testbenches in smtbmc
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2017-07-12 15:57:04 +02:00 |
Clifford Wolf
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4a8c131fa7
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Fix the fixed handling of x-bits in EDIF back-end
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2017-07-11 17:45:29 +02:00 |
Clifford Wolf
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479be3cec7
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Fix handling of x-bits in EDIF back-end
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2017-07-11 17:38:19 +02:00 |
Clifford Wolf
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9557fd2a36
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Add attributes and parameter support to JSON front-end
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2017-07-10 13:17:38 +02:00 |
Clifford Wolf
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8a69759306
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Add techlibs/xilinx/lut2lut.v
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2017-07-10 12:09:05 +02:00 |
Clifford Wolf
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4b2d1fe688
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Add JSON front-end
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2017-07-08 16:40:40 +02:00 |
Clifford Wolf
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3c693b6561
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Change s/asserts/assertions/ in yosys-smtbmc log messages
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2017-07-07 11:52:25 +02:00 |
Clifford Wolf
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8f7404f82c
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Add "yosys-smtbmc --presat"
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2017-07-07 02:47:30 +02:00 |
Clifford Wolf
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5442554e6f
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Fix generation of multiple outputs for same AIG node in write_aiger
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2017-07-05 14:23:54 +02:00 |
Clifford Wolf
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37af6294bd
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Add write_table command
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2017-07-05 12:13:53 +02:00 |
Clifford Wolf
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28039c3063
|
Add Verific Release information to log
|
2017-07-04 20:01:30 +02:00 |
Clifford Wolf
|
621787a9e0
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Fix some c++ clang compiler errors
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2017-07-03 19:38:30 +02:00 |
Clifford Wolf
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5c1c126374
|
Apply minor coding style changes to coolrunner2 target
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2017-07-03 19:35:40 +02:00 |
Clifford Wolf
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6afee022ad
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Merge pull request #352 from rqou/master
Initial Coolrunner-II support
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2017-07-03 19:33:36 +02:00 |
Clifford Wolf
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3f863c607a
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Merge pull request #356 from set-soft/clean-test
Added the test outputs to the clean target
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2017-07-03 19:33:25 +02:00 |
Clifford Wolf
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d223292aa9
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Merge pull request #355 from set-soft/exclude_TBUF_merge
Excluded $_TBUF_ from opt_merge pass
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2017-07-03 19:31:59 +02:00 |
Salvador E. Tropea
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fb30511044
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Added the test outputs to the clean target
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2017-07-03 13:33:11 -03:00 |
Salvador E. Tropea
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ca23554528
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Excluded $_TBUF_ from opt_merge pass
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2017-07-03 13:21:20 -03:00 |
Clifford Wolf
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3e0948e16f
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Remove unneeded delays in smtbmc vlogtb
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2017-07-03 15:37:17 +02:00 |
Clifford Wolf
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287831dca3
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Include output ports with constant driver in AIGER output
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2017-07-03 14:53:17 +02:00 |
Clifford Wolf
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ea805af6f5
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Add "yosys-smtbmc --vlogtb-top"
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2017-07-01 18:19:23 +02:00 |
Clifford Wolf
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0a02cdb93b
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Fix and_or_buffer optimization in opt_expr for signed operators
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2017-07-01 16:05:26 +02:00 |
Clifford Wolf
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7d2fb6e2fc
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Fix smtbmc vlogtb bug in $anyseq handling
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2017-07-01 02:13:32 +02:00 |
Clifford Wolf
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0f217080cf
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Add "design -import"
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2017-06-30 19:18:52 +02:00 |