Commit Graph

10894 Commits

Author SHA1 Message Date
github-actions[bot] d8fcf1ab25 Bump version 2021-08-08 00:50:48 +00:00
Marcelina Kościelnicka 98003430d6 opt_merge: Use FfInitVals.
Partial #2920 fix.
2021-08-08 01:19:22 +02:00
github-actions[bot] a24906a7d2 Bump version 2021-08-07 00:45:55 +00:00
Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types.
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
2021-08-06 21:35:43 +02:00
github-actions[bot] 2e421feb0e Bump version 2021-08-05 00:51:08 +00:00
Marcelina Kościelnicka 63f9e0544f memory_share: Don't skip ports with EN wired to input for SAT sharing.
Fixes #2912.
2021-08-04 04:47:43 +02:00
github-actions[bot] d8b0c3277f Bump version 2021-08-04 00:49:53 +00:00
Marcelina Kościelnicka 8733e1923a memory_bram: Move init data swizzling before other swizzling.
Fixes #2907.
2021-08-03 15:04:10 +02:00
github-actions[bot] ca8ad62696 Bump version 2021-08-03 00:55:22 +00:00
Miodrag Milanovic be04d8834e Require latest verific 2021-08-02 10:29:58 +02:00
github-actions[bot] 10bcc4e192 Bump version 2021-08-02 00:50:24 +00:00
Marcelina Kościelnicka ec2a468bd3 backend/verilog: Add alternate mode for transparent read port output.
This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
2021-08-01 19:11:29 +02:00
Marcelina Kościelnicka 4451f7f5e9 memory_bram: Some refactoring
This will make more sense when the new transparency masks land.

Fixes #2902.
2021-08-01 16:51:24 +02:00
github-actions[bot] 12db9b4273 Bump version 2021-07-31 00:50:30 +00:00
Miodrag Milanović c4a295cb8d
Update version.yml 2021-07-30 19:50:02 +02:00
Maciej Dudek cfddef5d7d Fixes xc7 BRAM36s
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-07-30 16:17:22 +02:00
Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00
Zachary Snow 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00
github-actions[bot] 87ef1dd805 Bump version 2021-07-30 00:52:33 +00:00
Marcelina Kościelnicka 54e75129e5 opt_lut: Allow more than one -dlogic per cell type.
Fixes #2061.
2021-07-29 17:30:07 +02:00
Zachary Snow 3156226233 verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
github-actions[bot] a055145b95 Bump version 2021-07-29 00:49:14 +00:00
Marcelina Kościelnicka 8bdc019730 verilog: Emit $meminit_v2 cell.
Fixes #2447.
2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka e9effd58d2 backends/verilog: Support meminit with mask. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
github-actions[bot] 37d76deef1 Bump version 2021-07-28 00:52:46 +00:00
Marcelina Kościelnicka a0e912ba99 proc: Run opt_expr at the end 2021-07-27 20:44:45 +02:00
Marcelina Kościelnicka 436d42c00c opt_expr: Propagate constants to port connections.
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value.  This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
2021-07-27 20:44:26 +02:00
github-actions[bot] 9600f20be8 Bump version 2021-07-27 00:52:14 +00:00
Miodrag Milanovic 45968ad740 Add version bump workflow 2021-07-26 11:25:32 +02:00
Miodrag Milanovic 987fca5297 Update to latest verific 2021-07-21 09:46:53 +02:00
Rupert Swarbrick 7a25246a7e Use new read_id_num helper function elsewhere in hierarchy.cc 2021-07-20 10:13:15 -04:00
Rupert Swarbrick 8fd6b45a3c Extract connection checking logic from expand_module in hierarchy.cc
No functional change, but pulls more logic out of the expand_module
function.
2021-07-20 10:13:15 -04:00
whitequark a04844bdf8
Merge pull request #2885 from whitequark/cxxrtl-fix-2883
cxxrtl: treat wires with multiple defs as not inlinable
2021-07-20 13:12:11 +00:00
whitequark 72beee2ccc
Merge pull request #2884 from whitequark/cxxrtl-fix-2882
cxxrtl: treat assignable internal wires used only for debug as locals
2021-07-20 13:12:03 +00:00
whitequark 1a6ddf7892 cxxrtl: treat wires with multiple defs as not inlinable.
Fixes #2883.
2021-07-20 10:30:39 +00:00
whitequark 225af830c1 cxxrtl: treat assignable internal wires used only for debug as locals.
This issue was introduced in commit 4aa65f40 while fixing #2739.

Fixes #2882.
2021-07-20 10:10:42 +00:00
whitequark c2afcbe78d
Merge pull request #2881 from whitequark/cxxrtl-sideways-colon
cxxrtl: escape colon in variable names in VCD writer
2021-07-20 09:30:08 +00:00
whitequark fc84f23001 cxxrtl: escape colon in variable names in VCD writer.
The following VCD file crashes GTKWave's VCD loader:

    $var wire 1 ! x:1 $end
    $enddefinitions $end

In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:

    update$func$.../hdl/hazard3_csr.v:350$2534.$result
2021-07-19 16:22:55 +00:00
whitequark 9af88951bc
Merge pull request #2880 from whitequark/cxxrtl-fix-2877
cxxrtl: add debug_item::{get,set}
2021-07-18 07:35:23 +00:00
whitequark 948fc10d7b cxxrtl: add debug_item::{get,set}.
Fixes #2877.
2021-07-18 06:20:45 +00:00
whitequark 101d72ccb3
Merge pull request #2879 from whitequark/cxxrtl-fix-2739-again
cxxrtl: treat internal wires used only for debug as constants
2021-07-17 17:22:15 +00:00
whitequark 4aa65f406f cxxrtl: treat internal wires used only for debug as constants.
Fixes #2739 (again).
2021-07-17 14:23:57 +00:00
Rupert Swarbrick 414154dd27 Add support for parsing the SystemVerilog 'bind' construct
This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
2021-07-16 09:31:39 -04:00
whitequark 2db4137514
Merge pull request #2874 from whitequark/cxxrtl-fix-2589
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
2021-07-16 11:12:19 +00:00
whitequark efc43270fa
Merge pull request #2873 from whitequark/cxxrtl-fix-2500
cxxrtl: emit debug items for unused public wires
2021-07-16 11:01:10 +00:00
whitequark 37f5ed9439
Merge pull request #2872 from whitequark/cxxrtl-fix-2521
cxxrtl: don't expect user cell inputs to be wires
2021-07-16 10:34:30 +00:00
whitequark 5b003d6e5c cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.
The hierarchy pass does a lot more than just finding the top module,
mainly resolving implicit (positional, wildcard) module connections.

Fixes #2589.
2021-07-16 10:27:47 +00:00
whitequark 09218896d6 cxxrtl: emit debug items for unused public wires.
This greatly improves debug information coverage.

Fixes #2500.
2021-07-16 10:14:40 +00:00
whitequark b28ca7f5ac cxxrtl: don't expect user cell inputs to be wires.
Ports can be connected to constants, too. (Usually resets.)

Fixes #2521.
2021-07-16 09:51:52 +00:00