Commit Graph

1375 Commits

Author SHA1 Message Date
N. Engelhardt 43780c9812
Merge pull request #3838 from povik/various-cleanup 2023-07-24 16:24:23 +02:00
Martin Povišer 51ef942547 verilog_backend: Use hashlib dict for `auto_name_map`
This is most likely faster.
2023-07-20 21:00:33 +01:00
Martin Povišer 596743a6b6 verilog_backend: Make the keywords pool static
Do not recreate the keywords pool on every lookup of an identifier.
2023-07-20 21:00:33 +01:00
Martin Povišer 78d13d1956 Mention 'bwmuxmap' in 'write_firrtl' help
The FIRRTL backend does call into the 'bwmuxmap' pass but omits it in
the help message.
2023-07-10 12:45:03 +02:00
Martin Povišer c0b1a7daa4 Drop stray 'cellaigs.h' include from backend passes
This include seems to have been copied over from the JSON backend where
AIG models are sometimes inserted into the JSON output, but these other
backends don't do anything with AIG.
2023-07-10 12:45:03 +02:00
Martin Povišer 06256c0c00 Slightly adjust the wording of "write_blif" help 2023-07-10 12:41:43 +02:00
Charlotte eb397592f0 cxxrtl: add `$divfloor`. 2023-06-28 15:27:06 +01:00
Jannis Harder 596da3f2a6
Merge pull request #3815 from charlottia/py312-syntax 2023-06-26 16:36:58 +02:00
Jannis Harder f9744fdfcd smtbmc: Make cover mode respect --keep-going
As cover mode by default stops looking for further traces when an
assertion fails, it should respect --keep-going.
2023-06-23 10:27:38 +02:00
Charlotte 3f29bdbbc5 smt2: py3.12+: avoid SyntaxWarning.
Python 3.12 emits a SyntaxWarning when encountering invalid escape
sequences.  They still parse as expected.  Marking these raw produces
the same result without the warnings.
2023-06-23 14:40:02 +10:00
Clifford Wolf cff3195caa Improve EDIF lib_cell_ports scan 2023-06-20 10:42:05 +02:00
Clifford Wolf fb9e12761b Add "write_edif -lsbidx" 2023-06-20 10:40:15 +02:00
Charlotte Connor c9d31c3c87 smt2: abits needs to be at least 1 for BitVec
BitVecs need a minimum length of 1; we zero-fill any extra bits in the
extend_u0() calls which works perfectly.
2023-06-13 15:01:45 +10:00
Jannis Harder 06f06c7be2
Merge pull request #3801 from jix/witness-aiw2yw-xbits 2023-06-12 16:12:39 +02:00
Jannis Harder dcc4d6e90b yosys-witness: Don't treat aiw x-bits as don't change
While treating initialization only bits as don't change during later
cycles is correct, actual x-bits should be kept as x-bits.
2023-06-09 15:21:22 +02:00
N. Engelhardt 6f5d984bdb
Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00
Claire Xenia Wolf d7f25165a5 Add ninitff line to aiger .aim files
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-06-03 14:38:22 +02:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
2023-05-25 12:48:02 +02:00
Jannis Harder 4f3d1be96a
Merge pull request #3767 from YosysHQ/krys/yw_fix
Assign wires an smtoffset
2023-05-22 16:10:55 +02:00
Jannis Harder 5fb1223861
Merge pull request #3733 from AdamHillier/aiger-inputs
Add outputs before inputs to the sigmap in the AIGER backend.
2023-05-22 16:09:15 +02:00
Jannis Harder e6f3914800 smt2: Use smt bv offset for `$any*`'s smtoffset
While not setting the smtoffset here was clearly a bug, I think using
`chunk.offset` only worked incidentally. The `smtoffset` is an offset
into the `smtname, smtid` pair (here `"", idcounter`) which corresponds
to the smt bitvector `stringf("%s#%d", get_id(module), idcounter)` which
contains all the chunks this loop is iterating over.

Thus using an incrementing `smtoffset` (like the `$ff`/`$dff` case above
already does) should be the correct fix.
2023-05-18 11:58:09 +02:00
Krystine Sherwin 52ad7a47f3
Assign wires an smtoffset
Wires weren't being assigned an smtoffset value so when generating a yosys witness trace it would also use an offset of 0.
Not sure if this has any other effects, but it fixes the bug I was having.
@jix could you take a look at this?
2023-05-18 10:37:55 +12:00
Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670)
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
AdamHillier 3861cc31f0 Add outputs before inputs to the sigmap in the AIGER backend. 2023-04-19 11:00:51 +00:00
Catherine 4bb173e256 yosys-smtbmc: support -h/--help (and exit with code 0). 2023-02-27 20:31:00 +00:00
Jannis Harder 160eeab2bb verilog_backend: Do not run bwmuxmap even if in expr mode
While bwmuxmap generates equivalent logic, it doesn't propagate x bits
in the same way, which can be relevant when writing verilog.
2023-02-13 14:00:38 +01:00
Aki Van Ness a90f940615 backends/firrtl: Ensure `modInstance` is valid
This should fix #3648 where when calling `emit_elaborated_extmodules` it
checks to see if a module is a black-box, however there was no
validation that the cell type was actually known, and it just always
assumed that we would get a valid instance, causing a segfault.
2023-02-03 08:27:52 -05:00
Jannis Harder 0f2cb80a26
Merge pull request #3655 from jix/smt2_fix_b_op_width
smt2: Fix operation width computation for boolean producing cells
2023-02-01 18:06:59 +01:00
Jannis Harder 5e82638408 smt2: Fix operation width computation for boolean producing cells
The output width for the boolean value should not influence the
operation width. The previous incorrect width extension would still
produce correct results, but could produce invalid smt2 output for
reduction operators when the output width was larger than the width of
the vector to which the reduction was applied.

This fixes #3654
2023-02-01 12:34:35 +01:00
Jannis Harder b08a880704 backends/rtlil: Do not shorten a value with z bits to 'x 2023-01-29 14:02:25 +01:00
Miodrag Milanović 8180cc4325
Merge pull request #3624 from jix/sim_yw
Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
2023-01-11 18:07:16 +01:00
Jannis Harder 636b9f2705 Support for BTOR witness to Yosys witness conversion 2023-01-11 18:07:16 +01:00
Jannis Harder 3e25e61778 aiger: Use new JSON code for writing aiger witness map files 2023-01-11 18:07:16 +01:00
Jannis Harder 673ad561b8 smt2: Treat bweqx as xnor
Without x-bits they are equivalent
2023-01-11 18:07:16 +01:00
Jannis Harder 62afe61779 smt2: Directly implement bwmux instead of using bwmuxmap 2023-01-11 18:07:16 +01:00
Jannis Harder be752a20dc Add bwmuxmap pass 2022-11-30 18:50:53 +01:00
Jannis Harder f2c531e65f verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode. 2022-11-30 18:24:35 +01:00
Jannis Harder 82b630a246 verilog_backend: Correctly sign extend output of signed `$modfloor` 2022-11-30 18:24:35 +01:00
Jannis Harder 5cb7d0fe9d verilog_backend: Add -noparallelcase option 2022-11-30 18:24:35 +01:00
Jannis Harder 96029400cb smtbmc: Do not assume skipped assertions when loading a witness trace
This is not valid when the prefix of a trace already violates
assertions. This can happen when the trace generating solver doesn't
look for a minimal length counterexample.
2022-10-20 13:49:47 +02:00
Emil J 8859d801c8
Temporal induction counterexample loop detection (#3504)
I have added an optional flag to smtbmc that causes failed temporal induction counterexample traces to be checked for duplicate states and reported to the user, since loops in the counterexample mean that increasing the induction depth won't help prove a design's safety properties.
2022-10-19 12:20:12 +02:00
Jannis Harder 8838b1eaa4 smtbmc: Fix witness handling for k-induction failures
The "uninitialized" value is a _list_ of chunks that are part of the
initial state for the witness trace.
2022-10-18 19:51:36 +02:00
Jannis Harder 4d334fd3e3 smt2/smtbmc: Fix FF witness data for fine grained or multi chunk FFs
The witness metadata was missing fine grained FFs completely and for
coarse grained FFs where the output connection has multiple chunks it
lacked the offset of the chunk within the SMT expression. This fixes
both, the later by adding an "smtoffset" field to the metadata.
2022-10-12 19:48:36 +02:00
Aki Van Ness 7a73133c9f
backends: protobuf: removed protobuf backend 2022-10-10 10:41:11 -04:00
Jannis Harder 1d40f5e8fa smtbmc: Avoid unnecessary string copies when parsing solver output 2022-09-02 22:37:08 +02:00
KrystalDelusion 9465b2af95 Fitting help messages to 80 character width
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
2022-08-24 10:40:57 +12:00
Jannis Harder 5142fb3b5c write_aiger: Fix non-$_FF_ FFs
This broke while switching sby's formal flows to always use $_FF_'s.
2022-08-18 13:56:22 +02:00