mirror of https://github.com/YosysHQ/yosys.git
write_aiger: Fix non-$_FF_ FFs
This broke while switching sby's formal flows to always use $_FF_'s.
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1c36f4cc2c
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5142fb3b5c
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@ -202,7 +202,7 @@ struct AigerWriter
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ff_map[Q] = D;
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if (cell->type != ID($_FF_)) {
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auto sig_clk = sigmap(cell->getPort(ID::CLK).as_bit());
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auto sig_clk = sigmap(cell->getPort(ID::C).as_bit());
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ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
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}
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continue;
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@ -0,0 +1,7 @@
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read_verilog -icells <<EOT
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module top(input clk, d, output q);
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\$_DFF_N_ dffn(.C(clk), .D(d), .Q(q));
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endmodule
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EOT
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write_aiger -zinit -ywmap aiger_dff.out /dev/null
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!grep -qF negedge aiger_dff.out
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