mirror of https://github.com/YosysHQ/yosys.git
Improve EDIF lib_cell_ports scan
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@ -192,6 +192,14 @@ struct EdifBackend : public Backend {
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for (auto module : design->modules())
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{
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lib_cell_ports[module->name];
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for (auto port : module->ports)
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{
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Wire *wire = module->wire(port);
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lib_cell_ports[module->name][port] = std::max(lib_cell_ports[module->name][port], GetSize(wire));
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}
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if (module->get_blackbox_attribute())
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continue;
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@ -208,7 +216,7 @@ struct EdifBackend : public Backend {
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if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
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lib_cell_ports[cell->type];
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for (auto p : cell->connections())
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lib_cell_ports[cell->type][p.first] = GetSize(p.second);
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lib_cell_ports[cell->type][p.first] = std::max(lib_cell_ports[cell->type][p.first], GetSize(p.second));
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}
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}
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}
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