Marcelina Kościelnicka
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cd6f0732f3
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xilinx: Add FDRSE_1, FDCPE_1.
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2021-01-27 00:32:00 +01:00 |
whitequark
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a77fa6709b
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Merge pull request #2563 from whitequark/cxxrtl-msvc
cxxrtl: do not use `->template` for non-dependent names
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2021-01-26 21:55:12 +00:00 |
whitequark
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d73ffa07f2
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Merge pull request #2544 from modwizcode/fix-clock
CXXRTL: Fix sliced bits as clock inputs
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2021-01-26 21:18:06 +00:00 |
whitequark
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4b6e764c46
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cxxrtl: do not use `->template` for non-dependent names.
This breaks build on MSVC but not GCC/Clang.
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2021-01-26 18:09:53 +00:00 |
Yosys Bot
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8eaeaa8434
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Bump version
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2021-01-26 00:10:05 +00:00 |
whitequark
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f200a8fe1c
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Merge pull request #2549 from pgadfort/support-multiple-libs
adding support for passing multiple liberty files to abc
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2021-01-25 10:36:14 +00:00 |
whitequark
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ffbd813a8c
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Merge pull request #2550 from zachjs/macro-arg-spaces
verilog: allow spaces in macro arguments
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2021-01-25 10:36:07 +00:00 |
Yosys Bot
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410ea42242
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Bump version
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2021-01-25 00:10:07 +00:00 |
Claire Xen
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2257a9a721
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Merge pull request #2558 from YosysHQ/dave/chandle-dpi
dpi: Support for chandle type
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2021-01-24 02:45:08 +01:00 |
David Shah
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09311b6581
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dpi: Support for chandle type
Signed-off-by: David Shah <dave@ds0.me>
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2021-01-23 22:24:31 +00:00 |
Yosys Bot
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54294957ed
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Bump version
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2021-01-22 00:10:05 +00:00 |
Miodrag Milanović
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1f88a3de74
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Merge pull request #2553 from zachjs/rand-const-modifiers
Allow combination of rand and const modifiers
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2021-01-21 16:56:19 +01:00 |
Zachary Snow
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1096b969ef
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Allow combination of rand and const modifiers
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2021-01-21 08:42:05 -07:00 |
Yosys Bot
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699a98b265
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Bump version
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2021-01-21 00:10:05 +00:00 |
Claire Xen
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b734f2c932
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Merge pull request #2552 from YosysHQ/claire/yosyshq
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
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2021-01-21 00:54:45 +01:00 |
Claire Xenia Wolf
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acad7a6e40
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Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-01-20 20:48:10 +01:00 |
Miodrag Milanović
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bfa353f154
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Merge pull request #2536 from TobiasFaller/master
Fixed missing goto statement in passes/techmap/abc.cc
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2021-01-20 20:42:02 +01:00 |
Miodrag Milanović
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00f02e0589
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Merge pull request #2551 from zachjs/wire-logic
sv: fix support wire and var data type modifiers
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2021-01-20 18:31:49 +01:00 |
Zachary Snow
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006c18fc11
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sv: fix support wire and var data type modifiers
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2021-01-20 09:16:21 -07:00 |
Zachary Snow
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4fadcc8f25
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verilog: allow spaces in macro arguments
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2021-01-20 08:49:58 -07:00 |
Yosys Bot
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4762cc06c6
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Bump version
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2021-01-19 00:10:05 +00:00 |
Peter Gadfort
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169234d6e9
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adding support for passing multiple liberty files to abc
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2021-01-18 16:47:49 -05:00 |
whitequark
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e991ceeef3
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Merge pull request #2547 from zachjs/plugin-so-dsym
Add plugin.so.dSYM to .gitignore
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2021-01-18 20:21:20 +00:00 |
whitequark
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056c12eb6f
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Merge pull request #2312 from antmicro/typedef-inout
Add support for user types in IOs
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2021-01-18 20:20:52 +00:00 |
Zachary Snow
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4c108b4419
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Add plugin.so.dSYM to .gitignore
This artifact is automatically generated by the builtin clang on macOS
when -g is used.
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2021-01-18 11:13:21 -07:00 |
Kamil Rakoczy
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d69ddf19da
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Add typedef input/output test
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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2021-01-18 17:31:22 +01:00 |
Kamil Rakoczy
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61501e3266
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Fix input/output attributes when resolving typedef of wire
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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2021-01-18 17:31:22 +01:00 |
Lukasz Dalek
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09071afe15
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Parse package user type in module port list
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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2021-01-18 17:31:22 +01:00 |
Iris Johnson
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c8415884d1
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Improves the previous commit with a more complete coverage of the cases
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2021-01-15 13:59:20 -06:00 |
Yosys Bot
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339848b954
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Bump version
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2021-01-15 00:10:05 +00:00 |
Iris Johnson
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86607d0fdc
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Handle sliced bits as clock inputs (fixes #2542)
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2021-01-14 16:36:21 -06:00 |
Marcelina Kościelnicka
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01626e6746
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opt_share: Fix X and CO signal width for shifted $alu in opt_share.
These need to be the same length as actual Y, not visible part of Y.
Fixes #2538.
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2021-01-14 14:54:08 +01:00 |
Yosys Bot
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7cd044bbc4
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Bump version
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2021-01-14 00:10:05 +00:00 |
Claire Xen
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0927675147
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Merge pull request #2537 from pepijndevos/spice
Add buffer option to spice backend
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2021-01-13 19:08:25 +01:00 |
Pepijn de Vos
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e789a00557
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add buffer option to spice backend
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2021-01-13 17:24:28 +01:00 |
Tobias Faller
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760a2c1343
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Fixed missing goto statement in passes/techmap/abc.cc
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2021-01-12 16:17:51 +01:00 |
Yosys Bot
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b0004911ca
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Bump version
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2021-01-05 00:10:05 +00:00 |
whitequark
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b00e55a16a
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Merge pull request #2522 from tomverbeure/simlib_typos2
Fix some trivial typos.
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2021-01-04 14:04:17 +00:00 |
Tom Verbeure
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87637e8359
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Fix some trivial typos.
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2021-01-03 23:52:59 -08:00 |
Yosys Bot
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b72c294653
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Bump version
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2021-01-02 00:10:04 +00:00 |
whitequark
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b0d4c63957
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Merge pull request #2480 from YosysHQ/dave/nexus-lram
nexus: Add LRAM inference
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2021-01-01 09:49:00 +00:00 |
whitequark
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1387c3b41d
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Merge pull request #2512 from umarcor/plugin-err
plugin: enhance no-plugin error
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2021-01-01 09:39:17 +00:00 |
whitequark
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8759ed9883
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Merge pull request #2515 from umarcor/fix/ghdl
makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
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2021-01-01 09:37:12 +00:00 |
whitequark
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bc2de4567c
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Merge pull request #2518 from zachjs/recursion
verilog: improved support for recursive functions
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2021-01-01 09:32:26 +00:00 |
whitequark
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1a80194cd3
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Merge pull request #2517 from zachjs/sv-tf-implied-direction
sv: complete support for implied task/function port directions
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2021-01-01 09:31:49 +00:00 |
Zachary Snow
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2085d9a55d
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verilog: improved support for recursive functions
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2020-12-31 18:33:59 -07:00 |
Zachary Snow
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75abd90829
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sv: complete support for implied task/function port directions
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2020-12-31 16:17:13 -07:00 |
umarcor
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7f28afd3ac
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makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
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2020-12-30 07:06:52 +01:00 |
Yosys Bot
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48d0aeb094
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Bump version
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2020-12-30 00:10:06 +00:00 |
umarcor
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e61b107072
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plugin: enhance no-plugin error
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2020-12-29 05:50:04 +01:00 |