mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2522 from tomverbeure/simlib_typos2
Fix some trivial typos.
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b00e55a16a
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@ -237,7 +237,7 @@ endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $reduce_and (A, B, Y)
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//- $reduce_and (A, Y)
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//-
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//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.
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//-
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@ -264,7 +264,7 @@ endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $reduce_or (A, B, Y)
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//- $reduce_or (A, Y)
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//-
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//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.
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//-
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@ -291,7 +291,7 @@ endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $reduce_xor (A, B, Y)
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//- $reduce_xor (A, Y)
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//-
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//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.
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//-
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@ -318,7 +318,7 @@ endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $reduce_xnor (A, B, Y)
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//- $reduce_xnor (A, Y)
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//-
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//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.
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//-
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@ -345,7 +345,7 @@ endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $reduce_bool (A, B, Y)
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//- $reduce_bool (A, Y)
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//-
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//- An OR reduction. This cell type is used instead of $reduce_or when a signal is
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//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.
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