Robert Ou
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6e0fb889fa
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coolrunner2: Initial commit
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2017-06-24 07:22:56 -07:00 |
Clifford Wolf
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155a80dfb7
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Fix handling of init values in "abc -dff" and "abc -clk"
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2017-06-20 15:32:23 +02:00 |
Clifford Wolf
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1f517d2b96
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Fix history namespace collision
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2017-06-20 05:26:12 +02:00 |
Clifford Wolf
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c0ca99483c
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Store command history when terminating with an error
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2017-06-20 04:41:58 +02:00 |
Clifford Wolf
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f6421c83a2
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Switched abc "clock domain not found" error to log_cmd_error()
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2017-06-20 04:22:34 +02:00 |
Clifford Wolf
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8f8baccfde
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Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
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2017-06-07 12:30:24 +02:00 |
Clifford Wolf
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129984e115
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Fix handling of Verilog ~& and ~| operators
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2017-06-01 12:43:21 +02:00 |
Clifford Wolf
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0290b68a44
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Update ABC to hg rev efbf7f13ea9e
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2017-05-31 11:55:37 +02:00 |
Clifford Wolf
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e7a984a4df
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Add dff2ff.v techmap file
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2017-05-31 11:45:58 +02:00 |
Clifford Wolf
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c365e33fd7
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Fix AIGER back-end for multiple symbols per input/latch/output/property
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2017-05-30 19:09:11 +02:00 |
Clifford Wolf
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05df3dbee4
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Add "setundef -anyseq"
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2017-05-28 11:59:05 +02:00 |
Clifford Wolf
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9ed4c9d710
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Improve write_aiger handling of unconnected nets and constants
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2017-05-28 11:31:35 +02:00 |
Clifford Wolf
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d9201b85f3
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Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
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2017-05-27 11:56:01 +02:00 |
Clifford Wolf
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fad52abf70
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Add aliases for common sets of gate types to "abc -g"
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2017-05-24 11:39:05 +02:00 |
Clifford Wolf
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dca3b3cd5f
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Add examples/osu035
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2017-05-23 18:38:20 +02:00 |
Clifford Wolf
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664ba4d80e
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-05-23 18:24:27 +02:00 |
Clifford Wolf
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e0386d04f5
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Merge pull request #346 from azonenberg/master
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
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2017-05-23 14:07:30 +02:00 |
Andrew Zonenberg
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184bd148c9
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greenpak4_counters: Added support for parallel output from GP_COUNTx cells
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2017-05-22 19:39:55 -07:00 |
Clifford Wolf
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2122ae69b3
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Add workaround for CBMC bug to SimpleC back-end
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2017-05-17 21:07:54 +02:00 |
Clifford Wolf
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662a047815
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Enable readline and tcl in mxe builds
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2017-05-17 20:46:22 +02:00 |
Clifford Wolf
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6934b862d3
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Add missing AndnotGate() and OrnotGate() declarations to rtlil.h
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2017-05-17 19:10:57 +02:00 |
Clifford Wolf
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05cdd58c8d
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Add $_ANDNOT_ and $_ORNOT_ gates
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2017-05-17 09:08:29 +02:00 |
Clifford Wolf
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9f4fbc5e74
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Add <modname>_init() function generator to simpleC back-end
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2017-05-16 19:34:07 +02:00 |
Clifford Wolf
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35be567605
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Improve simplec back-end
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2017-05-16 08:50:23 +02:00 |
Clifford Wolf
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8d3c706459
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Improve simplec back-end
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2017-05-15 13:21:59 +02:00 |
Clifford Wolf
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9c397ea78b
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Improve simplec back-end
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2017-05-14 13:14:49 +02:00 |
Clifford Wolf
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628daab277
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Improve simplec back-end
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2017-05-13 18:47:31 +02:00 |
Clifford Wolf
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ef7594ce3d
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Improve simplec back-end
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2017-05-12 22:39:16 +02:00 |
Clifford Wolf
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7931e1ebb4
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Added support for more gate types to simplec back-end
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2017-05-12 17:42:31 +02:00 |
Clifford Wolf
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bd4ed19887
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Add first draft of simple C back-end
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2017-05-12 14:13:33 +02:00 |
Clifford Wolf
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241dc7dfb4
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Update ABC to hg rev e79576e10d72
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2017-05-11 10:32:32 +02:00 |
Clifford Wolf
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1a4b7c6bfa
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Fix boolector support in yosys-smtbmc
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2017-05-08 14:33:22 +02:00 |
Clifford Wolf
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e91548b33e
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Add support for localparam in module header
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2017-04-30 17:20:30 +02:00 |
Clifford Wolf
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3bbac5c141
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Fix equiv_simple, old behavior now available with "equiv_simple -short"
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2017-04-28 18:57:53 +02:00 |
Clifford Wolf
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f0db8ffdbc
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Add support for `resetall compiler directive
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2017-04-26 16:09:41 +02:00 |
Clifford Wolf
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b72a7e1104
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Replace CRLF line endings with LF in de2i.qsf (quartus example)
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2017-04-12 16:51:46 +02:00 |
Larry Doolittle
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2021ddecb3
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Squelch trailing whitespace
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2017-04-12 15:11:09 +02:00 |
Clifford Wolf
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41d4e91f38
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Add MAX10 and Cyclone IV items to CHANGELOG
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2017-04-07 10:01:28 +02:00 |
Clifford Wolf
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7791888703
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Merge pull request #337 from dh73/master
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
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2017-04-07 09:58:54 +02:00 |
dh73
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c27dcc1e47
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Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
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2017-04-05 23:01:29 -05:00 |
Clifford Wolf
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fcb274a564
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Add ConstEval defaultval feature
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2017-04-05 11:25:22 +02:00 |
Clifford Wolf
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dee4ec1661
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Fix gcc compiler warning
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2017-04-05 11:21:06 +02:00 |
Clifford Wolf
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b8d7f57f61
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Add front-end detection for *.tcl files
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2017-03-28 12:13:58 +02:00 |
Clifford Wolf
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58ee8e3b8a
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Add minisat 00_PATCH_typofixes.patch
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2017-03-27 14:37:00 +02:00 |
Clifford Wolf
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71cbe98a09
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Remove use of <fpu_control.h> in minisat
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2017-03-27 14:32:43 +02:00 |
Clifford Wolf
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106e44f406
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Add "write_smt2 -stdt" mode
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2017-03-20 12:00:35 +01:00 |
Clifford Wolf
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0ac72e759d
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Add generation of logic cells to EDIF back-end runtest.py
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2017-03-19 14:57:40 +01:00 |
Clifford Wolf
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850f8299a9
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Fix EDIF: portRef member 0 is always the MSB bit
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2017-03-19 14:53:28 +01:00 |
Clifford Wolf
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1390e9a0a7
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Add simple EDIF test case generator and checker
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2017-03-18 15:00:03 +01:00 |
Clifford Wolf
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088f9c9cab
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Fix verilog pre-processor for multi-level relative includes
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2017-03-14 17:30:20 +01:00 |