mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #346 from azonenberg/master
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
This commit is contained in:
Clifford Wolf
GitHub
commit
e0386d04f5
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@ -1,7 +1,7 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2016 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -89,24 +89,26 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
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struct CounterExtraction
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{
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int width; //counter width
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RTLIL::Wire* rwire; //the register output
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bool has_reset; //true if we have a reset
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RTLIL::SigSpec rst; //reset pin
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int count_value; //value we count from
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RTLIL::SigSpec clk; //clock signal
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RTLIL::SigSpec outsig; //counter output signal
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RTLIL::Cell* count_mux; //counter mux
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RTLIL::Cell* count_reg; //counter register
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RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
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int width; //counter width
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RTLIL::Wire* rwire; //the register output
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bool has_reset; //true if we have a reset
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RTLIL::SigSpec rst; //reset pin
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int count_value; //value we count from
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RTLIL::SigSpec clk; //clock signal
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RTLIL::SigSpec outsig; //counter output signal
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RTLIL::Cell* count_mux; //counter mux
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RTLIL::Cell* count_reg; //counter register
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RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
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pool<ModIndex::PortInfo> pouts; //Ports that take a parallel output from us
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};
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//attempt to extract a counter centered on the given cell
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//attempt to extract a counter centered on the given adder cell
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int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract)
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{
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SigMap& sigmap = index.sigmap;
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//GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
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//TODO: infer cascaded counters?
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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extract.width = a_width;
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if(a_width > 14)
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@ -213,10 +215,48 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
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//TODO: Verify count_reg CLK_POLARITY is 1
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//Register output must have exactly two loads, the inverter and ALU
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const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q"));
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//(unless we have a parallel output!)
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const RTLIL::SigSpec qport = count_reg->getPort("\\Q");
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const RTLIL::SigSpec cnout = sigmap(qport);
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pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
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if(cnout_loads.size() != 2)
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return 17;
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if(cnout_loads.size() > 2)
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{
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//It's OK to have other loads iff they go to a DAC or DCMP (these are POUT)
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for(auto c : cnout_loads)
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{
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if(c == underflow_inv)
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continue;
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if(c == cell)
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continue;
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//If the cell is not a DAC or DCMP, complain
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if( (c->type != "\\GP_DCMP") && (c->type != "\\GP_DAC") )
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return 17;
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//Figure out what port(s) are driven by it
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//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
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RTLIL::IdString portname;
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for(auto b : qport)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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for(auto x : ports)
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{
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if(x.cell != c)
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continue;
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if(portname == "")
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portname = x.port;
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//somehow our counter output is going to multiple ports
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//this makes no sense, don't allow inference
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else if(portname != x.port)
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return 17;
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}
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}
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//Save the other loads
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extract.pouts.insert(ModIndex::PortInfo(c, portname, 0));
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}
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}
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if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
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return 18;
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if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
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@ -312,7 +352,7 @@ void greenpak4_counters_worker(
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"Mux output is used outside counter", //14
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"Counter reg is not DFF/ADFF", //15
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"Counter input is not full bus", //16
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"Count register is used outside counter", //17
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"Count register is used outside counter, but not by a DCMP or DAC", //17
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"Register output is not full bus", //18
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"Register output is not full bus", //19
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"No init value found", //20
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@ -344,7 +384,7 @@ void greenpak4_counters_worker(
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//TODO: support other kind of reset
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reset_type = "async resettable";
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}
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log(" Found %d-bit %s down counter (from %d) for register %s declared at %s\n",
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log(" Found %d-bit %s down counter (counting from %d) for register %s declared at %s\n",
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extract.width,
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reset_type.c_str(),
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extract.count_value,
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@ -388,6 +428,19 @@ void greenpak4_counters_worker(
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cell->setPort("\\CLK", extract.clk);
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cell->setPort("\\OUT", extract.outsig);
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//Hook up any parallel outputs
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for(auto load : extract.pouts)
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{
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log(" Counter has parallel output to cell %s port %s\n", log_id(load.cell->name), log_id(load.port));
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//Find the wire hooked to the old port
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auto sig = load.cell->getPort(load.port);
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//Connect it to our parallel output
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//(this is OK to do more than once b/c they all go to the same place)
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cell->setPort("\\POUT", sig);
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}
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//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
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cells_to_remove.insert(extract.count_mux);
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cells_to_remove.insert(extract.count_reg);
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