Add examples/osu035

This commit is contained in:
Clifford Wolf 2017-05-23 18:38:20 +02:00
parent 664ba4d80e
commit dca3b3cd5f
4 changed files with 30 additions and 0 deletions

3
examples/osu035/.gitignore vendored Normal file
View File

@ -0,0 +1,3 @@
osu035_stdcells.lib
example.yslog
example.edif

13
examples/osu035/Makefile Normal file
View File

@ -0,0 +1,13 @@
example.edif: example.ys example.v osu035_stdcells.lib
yosys -l example.yslog -q example.ys
osu035_stdcells.lib:
rm -f osu035_stdcells.lib.part osu035_stdcells.lib
wget -O osu035_stdcells.lib.part https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/ami035/signalstorm/osu035_stdcells.lib
mv osu035_stdcells.lib.part osu035_stdcells.lib
clean:
rm -f osu035_stdcells.lib
rm -f example.yslog example.edif

View File

@ -0,0 +1,3 @@
module top (input clk, input [7:0] a, b, output reg [15:0] c);
always @(posedge clk) c <= a * b;
endmodule

View File

@ -0,0 +1,11 @@
read_verilog example.v
read_liberty -lib osu035_stdcells.lib
synth -top top
dfflibmap -liberty osu035_stdcells.lib
abc -liberty osu035_stdcells.lib
opt_clean
stat -liberty osu035_stdcells.lib
write_edif example.edif