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Add examples/osu035
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osu035_stdcells.lib
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example.yslog
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example.edif
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example.edif: example.ys example.v osu035_stdcells.lib
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yosys -l example.yslog -q example.ys
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osu035_stdcells.lib:
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rm -f osu035_stdcells.lib.part osu035_stdcells.lib
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wget -O osu035_stdcells.lib.part https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/ami035/signalstorm/osu035_stdcells.lib
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mv osu035_stdcells.lib.part osu035_stdcells.lib
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clean:
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rm -f osu035_stdcells.lib
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rm -f example.yslog example.edif
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module top (input clk, input [7:0] a, b, output reg [15:0] c);
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always @(posedge clk) c <= a * b;
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endmodule
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read_verilog example.v
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read_liberty -lib osu035_stdcells.lib
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synth -top top
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dfflibmap -liberty osu035_stdcells.lib
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abc -liberty osu035_stdcells.lib
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opt_clean
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stat -liberty osu035_stdcells.lib
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write_edif example.edif
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