Eddie Hung
cb24d23b6d
Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces
2019-05-21 18:20:58 -07:00
Eddie Hung
7057753427
Rename label
2019-05-21 18:20:31 -07:00
Eddie Hung
b5a29460b9
Try again
2019-05-21 17:20:19 -07:00
Eddie Hung
1bff09f2ff
Fix warning
2019-05-21 16:26:20 -07:00
Jim Lawson
a5131e2896
Fix static shift operands, neg result type, minor formatting
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Static shift operands must be constants.
The result of FIRRTL's neg operator is signed.
Fix poor indentation for gen_read().
2019-05-21 13:04:56 -07:00
Jim Lawson
489c555b41
Merge remote-tracking branch 'upstream/master'
2019-05-21 12:47:55 -07:00
Clifford Wolf
c4b8575f43
Add "wreduce -keepdc", fixes #1016
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
Clifford Wolf
c907899422
Merge pull request #1017 from Kmanfi/bigger_verilog_files
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Read bigger Verilog files.
2019-05-18 16:54:47 +02:00
Kaj Tuomi
48ddbe52fb
Read bigger Verilog files.
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Hit parser limit with 3M gate design. This commit fix it.
2019-05-18 14:20:30 +03:00
Clifford Wolf
b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes
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Support for attributes on parameters and localparams for Verilog frontend
2019-05-16 14:21:18 +02:00
Maciej Kurc
1f52332b8d
Added tests for Verilog frontent for attributes on parameters and localparams
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00
Maciej Kurc
ce4a0954bc
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:44:16 +02:00
Clifford Wolf
c9def5407c
Merge pull request #1012 from YosysHQ/clifford/sigspecrw
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Another rounds of opt_clean improvements
2019-05-15 21:00:56 +02:00
Clifford Wolf
a21a84b3b4
Improvements in opt_clean
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:28 +02:00
Clifford Wolf
287de4b848
Add rewrite_sigspecs2, Improve remove() wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00
Clifford Wolf
f67ec1b235
Do not leak file descriptors in cover.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 13:51:02 +02:00
Clifford Wolf
4fd0e11214
Merge pull request #1011 from hzeller/fix-constructing-string-from-int
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Fix two instances of integer-assignment to string.
2019-05-15 13:35:52 +02:00
Clifford Wolf
64b604207d
Merge pull request #1010 from hzeller/yacc-self-contained
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Make the generated *.tab.hh include all the headers needed
2019-05-15 13:29:55 +02:00
Clifford Wolf
36841f3911
Merge pull request #1008 from thasti/fix_libyosys_build
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Create $(LIBDIR) to fix broken build in isolated environments
2019-05-15 13:28:52 +02:00
David Shah
3ef88ffbb2
Merge pull request #1005 from smunaut/ice40_hfosc_trim
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ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
2019-05-15 08:20:50 +01:00
Henner Zeller
5e443a5d0d
Fix two instances of integer-assignment to string.
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o In cover.cc, the int-result of mkstemps() was assigned to a string
and silently interpreted as a single-character filename with a funny
value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
visible constructors, this is ambiguous. Explicitly cast this to
a char.
2019-05-14 22:01:15 -07:00
Henner Zeller
8eb2798776
Make the generated *.tab.hh include all the headers needed to define the union.
2019-05-14 21:07:26 -07:00
Stefan Biereigel
c97c860303
extract python prefix to allow overriding
2019-05-14 15:28:03 +02:00
Stefan Biereigel
660e733bd2
remove ldconfig call
2019-05-14 14:49:40 +02:00
Stefan Biereigel
6c9c78d4aa
add mkdir for libyosys target, explicitly copy to target folder
2019-05-14 14:36:31 +02:00
whitequark
c8c1df23a0
bugpoint: check for -script option.
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Fixes #925 .
2019-05-14 10:48:06 +00:00
Sylvain Munaut
4f9183d107
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-05-13 12:51:06 +02:00
Clifford Wolf
5772732a6d
Merge pull request #1004 from YosysHQ/clifford/fix1002
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Fix handling of glob_abort_cnt in opt_muxtree
2019-05-12 15:33:53 +02:00
Clifford Wolf
8166a142dd
Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-12 13:51:12 +02:00
Clifford Wolf
faf00586d8
Merge pull request #1003 from makaimann/zinit-all
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Zinit option '-singleton' -> '-all'
2019-05-11 13:56:51 +02:00
Clifford Wolf
b66b657b6b
Add "fmcombine -initeq -anyeq"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:28:55 +02:00
Clifford Wolf
04ef222cfb
Add "stat -tech xilinx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Makai Mann
2f5cfa014b
Zinit option '-singleton' -> '-all'
2019-05-10 10:23:14 -07:00
Clifford Wolf
9b2b0d91d2
Merge pull request #1000 from bwidawsk/synth-format
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Add clang format, and use on intel_synth (v2)
2019-05-09 18:41:38 +02:00
Ben Widawsky
05d8cc4567
Fix formatting for synth_intel.cc
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This is realized through the recently added .clang-format file.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-09 08:40:05 -07:00
Ben Widawsky
02e7d931a7
Add a .clang-format
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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-09 08:40:05 -07:00
Clifford Wolf
05a5027db8
Add $stop to documentation
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-09 15:31:40 +02:00
Jakob Wenzel
f06cb75b93
initialize more registers in setundef -init
2019-05-09 12:47:16 +02:00
Clifford Wolf
caad497839
Remove added newline (by re-running minisat 00_UPDATE.sh)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-08 11:26:58 +02:00
Clifford Wolf
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
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Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
Clifford Wolf
c582a25bdb
Merge pull request #998 from mdaiter/get_bool_attribute_opts
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Minor optimization to get_attribute_bool
2019-05-08 08:34:35 +02:00
Matthew Daiter
6e629d2895
Minor optimization to get_attribute_bool
2019-05-07 22:04:28 -05:00
Clifford Wolf
b7ec698d40
Add test case from #997
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:58:04 +02:00
Clifford Wolf
33738c1745
Fix handling of partial init attributes in write_verilog, fixes #997
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:55:36 +02:00
Clifford Wolf
0ee1759f00
Merge pull request #996 from mdaiter/ceil_log2_opts
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Optimize ceil_log2 function
2019-05-07 19:46:27 +02:00
Matthew Daiter
bafbb9ee90
Optimize ceil_log2 function
2019-05-07 12:17:56 -05:00
Clifford Wolf
09467bb9a3
Add "synth_xilinx -arch"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 15:04:36 +02:00
Clifford Wolf
a76189e7ad
More opt_clean cleanups
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 14:41:58 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00