riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,719 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

39 Commits

Author SHA1 Message Date
Eddie Hung c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00
Eddie Hung d21262ee04 Adding (* techmap_autopurge *) to FD* in abc9_map.v 2020-01-14 12:22:21 -08:00
Eddie Hung 98ee8c14df Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
Eddie Hung 50b68777d3 Drive $[ABCD] explicitly 2020-01-02 13:28:37 -08:00
Eddie Hung ec1756c094 Update comments 2020-01-02 12:39:52 -08:00
Eddie Hung 8e507bd807 abc9 -keepff -> -dff; refactor dff operations 2020-01-02 12:36:54 -08:00
Eddie Hung db04161eca Rework abc9's DSP48E1 model 2020-01-01 17:30:26 -08:00
Eddie Hung c40b1aae42 Restore abc9 -keepff 2020-01-01 08:34:43 -08:00
Eddie Hung 44d9fb0e7c Re-arrange FD order 2019-12-31 18:47:38 -08:00
Eddie Hung 35c659be74 Cleanup xilinx boxes 2019-12-31 18:29:44 -08:00
Eddie Hung 789211d9b3 Fix incorrect $__ABC9_ASYNC[01] box 2019-12-31 11:13:50 -08:00
Eddie Hung a038294a87 Tidy up abc9_map.v 2019-12-30 14:19:29 -08:00
Eddie Hung d7ada66497 Add "synth_xilinx -dff" option, cleanup abc9 2019-12-30 14:13:16 -08:00
Eddie Hung 7928eb113c Add RAM{32,64}M to abc9_map.v 2019-12-20 13:41:23 -08:00
Eddie Hung 45f0f1486b Add RAM{32,64}M to abc9_map.v 2019-12-19 11:24:39 -08:00
Eddie Hung 979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung 9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung 3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Eddie Hung c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung 864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Eddie Hung 0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung 19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung 31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
Eddie Hung a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung f98aa1c13f Revert "Add INIT value to abc9_control" 
This reverts commit 19bfb41958.
 2019-12-03 15:40:44 -08:00
Eddie Hung 19bfb41958 Add INIT value to abc9_control 2019-12-02 14:17:06 -08:00
Eddie Hung 6a2eb5d8f9 Special abc9_clock wire to contain only clock signal 2019-11-25 12:36:13 -08:00
Eddie Hung 5a30e3ac3b Merge branch 'eddie/xaig_dff_adff' into xaig_dff 2019-11-21 16:15:25 -08:00
Eddie Hung df63d75ff3 Fix INIT values 2019-11-20 11:26:59 -08:00
Eddie Hung 344619079d Do not drop async control signals in abc_map.v 2019-11-19 16:57:07 -08:00
Eddie Hung 4f0818275f Cleanup 2019-10-07 15:58:55 -07:00
Eddie Hung b2e34f932a Rename $currQ to $abc9_currQ 2019-10-07 15:31:43 -07:00
Eddie Hung bae3d8705d Update comments in abc9_map.v 2019-10-07 12:54:45 -07:00
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00