riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,391 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

288 Commits

Author SHA1 Message Date
Eddie Hung 587872236e Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
Eddie Hung 4e6c5e4672 Add binary AIGs converted from AAG 2019-02-08 11:41:25 -08:00
Eddie Hung 4167b15de5 Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig 2019-02-06 14:31:11 -08:00
Eddie Hung 3f87cf86cc Revert most of autotest.sh; for non *.v use Yosys to translate 2019-02-06 14:30:19 -08:00
Eddie Hung 115883f467 Add tests for simple cases using defparam 2019-02-06 14:15:17 -08:00
Eddie Hung 281f2aadca Add -B option to autotest.sh to append to backend_opts 2019-02-06 14:14:55 -08:00
Eddie Hung 03cf1532a7 Extend testcase 2019-02-06 14:02:11 -08:00
Eddie Hung a9674bd2ec Add testcase 2019-02-06 12:49:30 -08:00
Eddie Hung fdd55d064b Rename ASCII tests 2019-02-06 12:20:36 -08:00
Eddie Hung 3f0bb441f8 Add tests 2019-02-04 16:46:24 -08:00
Clifford Wolf 9666cca9dd Remove asicworld tests for (unsupported) switch-level modelling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-27 09:17:02 +01:00
Clifford Wolf 0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp 
opt_expr: refactor and improve simplification of comparisons
 2019-01-02 17:34:04 +01:00
whitequark bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
 2019-01-02 15:45:28 +00:00
whitequark a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark 4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark 9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark 8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1. 
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
 2019-01-02 02:45:49 +00:00
whitequark 42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Larry Doolittle 99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Clifford Wolf 2a681909df
Merge pull request #724 from whitequark/equiv_opt 
equiv_opt: new command, for verifying optimization passes
 2018-12-16 15:54:26 +01:00
whitequark 7ff5a9db2d equiv_opt: pass -D EQUIV when techmapping. 
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
 2018-12-07 17:20:34 +00:00
whitequark c38ea9ae65 equiv_opt: new command, for verifying optimization passes. 2018-12-07 17:20:34 +00:00
whitequark 7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
Clifford Wolf 7d1088afc4 Add missing .gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:37 +01:00
whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
whitequark 45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark 9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf 6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error 
More meaningful SystemVerilog/Verilog parser error messages
 2018-10-25 13:18:59 +02:00
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Udi Finkelstein 106af19b69 Fixed typo (sikp -> skip) 2018-06-05 22:41:27 +03:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Udi Finkelstein 80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files 2018-06-05 18:00:06 +03:00
Johnny Sorocil 0295213bec autotest.sh: Change from /bin/bash to /usr/bin/env bash 
This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).
 2018-05-06 15:26:23 +02:00
Clifford Wolf 5e49ee5c2d Fix tests/simple/specify.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:34:00 +02:00
Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf 25e33d7ab8 Major redesign of Verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-27 20:33:15 +01:00
Clifford Wolf 6d12c83d36 Add support for SVA throughout via Verific 2018-02-21 13:09:47 +01:00
Clifford Wolf 5c6247dfa6 Add support for SVA sequence concatenation ranges via verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 16:35:06 +01:00
Clifford Wolf 9d963cd29c Add support for SVA until statements via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 14:57:52 +01:00
Clifford Wolf bc8ab3ab44 Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF 2018-02-15 15:26:37 +01:00
Clifford Wolf baddb017fe Remove PSL example from tests/sva/ 2017-10-20 13:16:24 +02:00
Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Udi Finkelstein e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein 6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00