Eddie Hung
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b4663a987b
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Fix attributes on $__ABC9_ASYNC[01] whitebox
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2019-12-31 11:14:11 -08:00 |
Eddie Hung
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789211d9b3
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Fix incorrect $__ABC9_ASYNC[01] box
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2019-12-31 11:13:50 -08:00 |
Eddie Hung
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134e70e8e7
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write_xaiger: be more precise with ff_bits, remove ff_aig_map
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2019-12-31 10:21:11 -08:00 |
Eddie Hung
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3798fa3bea
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Retry getting rid of write_xaiger's holes_mode
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2019-12-31 09:59:17 -08:00 |
Eddie Hung
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436c96e2fb
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Revert "Get rid of holes_mode"
This reverts commit 7997e2a90f .
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2019-12-30 23:29:14 -08:00 |
Eddie Hung
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7997e2a90f
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Get rid of holes_mode
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2019-12-30 20:15:09 -08:00 |
Eddie Hung
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0c4be94a02
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Add -D DFF_MODE to abc9_map test
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2019-12-30 20:13:25 -08:00 |
Eddie Hung
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4c3f517425
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Remove delay targets doc
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2019-12-30 16:11:42 -08:00 |
Eddie Hung
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0735572934
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write_xaiger to use scratchpad for stats; cleanup abc9
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2019-12-30 15:35:33 -08:00 |
Eddie Hung
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fc4b8b8991
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Remove submod changes
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2019-12-30 14:56:14 -08:00 |
Eddie Hung
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d1fccd5a2d
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Remove unused
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2019-12-30 14:35:52 -08:00 |
Eddie Hung
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eb4e767053
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Do not offset FD* box timings due to -46ps Tsu
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2019-12-30 14:35:10 -08:00 |
Eddie Hung
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3cbbae251f
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Call "proc" if processes inside whiteboxes
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2019-12-30 14:33:05 -08:00 |
Eddie Hung
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405e974fe5
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-30 14:31:42 -08:00 |
Eddie Hung
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ece423415c
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Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md
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2019-12-30 14:24:58 -08:00 |
Eddie Hung
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a038294a87
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Tidy up abc9_map.v
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2019-12-30 14:19:29 -08:00 |
Eddie Hung
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d7ada66497
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Add "synth_xilinx -dff" option, cleanup abc9
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2019-12-30 14:13:16 -08:00 |
Eddie Hung
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52a27700e2
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Grammar
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2019-12-30 12:26:39 -08:00 |
Miodrag Milanović
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c0a17c2457
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Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
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2019-12-30 20:34:31 +01:00 |
Eddie Hung
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c2c74f9bb0
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Merge pull request #1599 from YosysHQ/eddie/retry_1588
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
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2019-12-30 10:01:02 -08:00 |
Eddie Hung
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ce6e4f6341
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Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
Nitpick cleanup for ecp5
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2019-12-30 10:00:47 -08:00 |
Miodrag Milanovic
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f9749c202c
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Fix new tests
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2019-12-28 16:43:19 +01:00 |
Miodrag Milanovic
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8c3de1d4bd
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Merge remote-tracking branch 'origin/master' into iopad_default
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2019-12-28 16:23:31 +01:00 |
Miodrag Milanovic
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a82c701668
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
Miodrag Milanovic
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509da7ed1a
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Revert "Fix xilinx tests, when iopads are default"
This reverts commit 477e43d921 .
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2019-12-28 16:12:45 +01:00 |
Eddie Hung
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011f749ecf
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Update resource count
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2019-12-28 02:15:11 -08:00 |
Eddie Hung
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71906fab51
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Nitpick cleanup for ecp5
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2019-12-27 16:57:08 -08:00 |
Eddie Hung
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d45869855c
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Add #1598 testcase
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2019-12-27 16:44:57 -08:00 |
Eddie Hung
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237415e78c
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write_xaiger: inherit port ordering from original module
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2019-12-27 16:44:18 -08:00 |
Eddie Hung
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a56d6970f2
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Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
This reverts commit 92654f73ea , reversing
changes made to 3e14ff1667 .
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2019-12-27 16:05:58 -08:00 |
Eddie Hung
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9e6632c40a
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Merge branch 'master' of github.com:YosysHQ/yosys
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2019-12-27 15:37:26 -08:00 |
Eddie Hung
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3d4644804e
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write_xaiger: simplify c{i,o}_bits
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2019-12-27 15:37:17 -08:00 |
David Shah
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92654f73ea
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Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup
Revert "write_xaiger: only instantiate each whitebox cell type once"
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2019-12-27 23:31:51 +00:00 |
David Shah
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df31ade3b3
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Revert "write_xaiger: only instantiate each whitebox cell type once"
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2019-12-27 23:25:20 +00:00 |
Eddie Hung
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dd503a5f3f
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Really fix it!
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2019-12-27 15:18:55 -08:00 |
Eddie Hung
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49881b4468
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write_xaiger: fix arrival times for non boxes
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2019-12-27 11:30:18 -08:00 |
Miodrag Milanovic
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3e14ff1667
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fixed invalid char
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2019-12-25 20:38:48 +01:00 |
Marcin Kościelnicki
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a24596def3
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iopadmap: Emit tristate buffers with const OE for some edge cases.
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2019-12-25 17:37:58 +01:00 |
Marcin Kościelnicki
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13a3041030
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Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-25 16:18:44 +01:00 |
Marcin Kościelnicki
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e226a8f7f1
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Minor nit fixes
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2019-12-25 15:39:40 +01:00 |
Eddie Hung
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2e21aa59a2
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Add DSP cascade tests
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2019-12-23 14:58:06 -08:00 |
Eddie Hung
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1d0ac659ad
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Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
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2019-12-23 14:40:59 -08:00 |
Eddie Hung
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75acaff6f5
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Fix CEA/CEB check
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2019-12-23 14:22:13 -08:00 |
Eddie Hung
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edabe73377
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Fix checking CE[AB] and for direct connections
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2019-12-23 13:41:26 -08:00 |
Eddie Hung
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71cac30309
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Support unregistered cascades for A and B inputs
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2019-12-23 12:38:18 -08:00 |
Eddie Hung
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d00533eaa8
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Add DSP48A* PCOUT -> PCIN cascade support
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2019-12-23 11:42:46 -08:00 |
Marcin Kościelnicki
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dadaf7ed78
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xilinx: Test our DSP48A/DSP48A1 simulation models.
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2019-12-23 20:36:43 +01:00 |
Eddie Hung
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509070f82f
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Disable clock domain partitioning in Yosys pass, let ABC do it
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2019-12-23 08:36:20 -08:00 |
Eddie Hung
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6eadd4390a
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write_xaiger to opt instead of just clean whiteboxes
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2019-12-23 08:35:53 -08:00 |
Marcin Kościelnicki
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666c6128a9
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |