69 Commits

Author	SHA1	Message	Date
Eddie Hung	037d1a03df	Add #1460 testcase	2019-12-12 17:49:55 -08:00
Eddie Hung	caab66111e	Rename memory tests to lutram, add more xilinx tests	2019-12-12 17:44:37 -08:00
Diego H	751a18d7e9	Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.	2019-12-12 17:32:58 -06:00
Eddie Hung	47ac1b01e6	Add test	2019-12-12 14:43:13 -08:00
Diego H	e33f407655	Adding a note (TODO) in the memory_params.ys check file	2019-12-12 16:06:46 -06:00
Diego H	937ec1ee78	Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1	2019-12-12 13:50:36 -06:00
Eddie Hung	a46a7e8a67	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-06 23:22:52 -08:00
Jan Kowalewski	dcb30b5f4a	tests: arch: xilinx: Change order of arguments in macc.sh	2019-12-06 09:15:49 +01:00
Eddie Hung	19bc429482	abc9_map.v to transform INIT=1 to INIT=0	2019-12-04 21:36:41 -08:00
Eddie Hung	de3476cc23	No need for -abc9	2019-11-26 23:08:14 -08:00
Eddie Hung	4a0198128e	Add citation	2019-11-26 22:51:16 -08:00
Eddie Hung	222e199b73	Add testcase derived from fastfir_dynamictaps benchmark	2019-11-26 21:26:30 -08:00
Marcin Kościelnicki	7562e7304e	xilinx: Use INV instead of LUT1 when applicable	2019-11-25 20:40:39 +01:00
Miodrag Milanovic	3e0ffe05a7	Fixed tests	2019-11-11 15:41:33 +01:00
Miodrag Milanovic	12383f37b2	Common memory test now shared	2019-10-18 12:33:35 +02:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00
Miodrag Milanovic	ab98f2dccf	fix yosys path	2019-10-18 11:18:53 +02:00
Miodrag Milanovic	56f9482675	Fix path to yosys	2019-10-18 11:12:03 +02:00
Miodrag Milanovic	c2ec7ca703	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00