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10595 Commits

Author SHA1 Message Date
Clifford Wolf f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf 34f34be17c Merge branch 'master' of https://github.com/rubund/yosys 2015-10-13 11:01:19 +02:00
Clifford Wolf eb1e3caae7 Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
Ruben Undheim 978933704b Use DESTDIR as defined in https://www.gnu.org/prep/standards/html_node/DESTDIR.html 
This is needed for painless packaging of yosys
 2015-10-11 00:56:20 +02:00
Ruben Undheim 2792b00792 Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when building 2015-10-11 00:47:37 +02:00
Clifford Wolf ba4cce9f19 Added support for "parameter" and "localparam" in global context 2015-10-07 14:59:08 +02:00
Clifford Wolf e51dcc83d0 Fixed complexity of assigning to vectors in constant functions 2015-10-01 12:15:35 +02:00
Clifford Wolf 9caeadf797 Fixed detection of unconditional $readmem[hb] 2015-09-30 15:46:51 +02:00
Clifford Wolf c58bd5dc30 Added edgetypes command 2015-09-27 11:53:20 +02:00
Clifford Wolf 281c1f4029 Some cleanups in qwp 2015-09-26 10:42:27 +02:00
Clifford Wolf ddcfc99f8c Added "test_cell -noeval" 2015-09-25 17:27:18 +02:00
Clifford Wolf 82028c42e0 Added wreduce $mul support and fixed signed $mul opt_const bug 2015-09-25 17:27:06 +02:00
Clifford Wolf 4864736167 Bugfix in bram read-enable code 2015-09-25 14:22:33 +02:00
Clifford Wolf f9d7df0869 Bugfixes in $readmem[hb] 2015-09-25 13:49:48 +02:00
Clifford Wolf 4ac202e2a5 Bugfixes in writing of memories as Verilog 2015-09-25 13:49:26 +02:00
Clifford Wolf b2544cfcf7 Fixed segfault in AstNode::asReal 2015-09-25 12:38:01 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf ec92c89659 Added pivoting to qwp solver 2015-09-24 22:16:37 +02:00
Clifford Wolf 69071bbc5f Improved qwp performance 2015-09-24 21:50:37 +02:00
Clifford Wolf b1e9cb332d Added statistics summary to "qwp" 2015-09-24 21:22:24 +02:00
Clifford Wolf 3501f8e364 Fixed memory_bram for ROMs in BRAMs with write-enable inputs 2015-09-24 11:37:15 +02:00
Clifford Wolf 1b8cb9940e Fixed AstNode::mkconst_bits() segfault on zero-sized constant 2015-09-24 11:21:20 +02:00
Clifford Wolf e2e092b144 Added read_verilog -nodpi 2015-09-23 08:23:38 +02:00
Clifford Wolf 089c1e176f Bugfix in handling of multi-dimensional memories 2015-09-23 07:56:17 +02:00
Clifford Wolf 559929e341 Warning for $display/$write outside initial block 2015-09-23 07:16:03 +02:00
Clifford Wolf b845b77f86 Fixed support for $write system task 2015-09-23 07:10:56 +02:00
Clifford Wolf a3a13cce32 Fixed detection of "task foo(bar);" syntax error 2015-09-22 21:34:21 +02:00
Clifford Wolf 6176f4d081 Fixed multi-level prefix resolving 2015-09-22 20:52:02 +02:00
Clifford Wolf 4b8200eb49 Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
Clifford Wolf 405cf67b64 Fixed emcc build 2015-09-21 12:33:36 +02:00
Clifford Wolf b66bf8bed1 Do not detect fsm state registers with init attribute 2015-09-21 11:54:00 +02:00
Clifford Wolf 11c27b5e69 Bugfix in "qwp" pass 2015-09-21 10:37:24 +02:00
Clifford Wolf 80898dcbc8 Improvements and fixes in "qwp" pass 2015-09-21 01:05:13 +02:00
Clifford Wolf 6329bea873 Added "qwp -dump" 2015-09-20 22:36:35 +02:00
Clifford Wolf 539c5eeb0f Added "qwp" command 2015-09-20 18:28:46 +02:00
Andrew Zonenberg c469f22144 Improvements to $display system task 2015-09-19 10:33:37 +02:00
Clifford Wolf 598a475724 Added nlutmap 2015-09-18 21:57:34 +02:00
Clifford Wolf c851f51656 Added lut2mux pass 2015-09-18 21:55:48 +02:00
Clifford Wolf d212d4d0c1 Cosmetic fix in Module::addLut() 2015-09-18 21:55:12 +02:00
Clifford Wolf db548800b6 Added buffer detection to "abc -lut" 2015-09-18 20:12:56 +02:00
Clifford Wolf 745d56149d Renamed GreenPAK4 cells, improved GP4 DFF mapping 2015-09-18 12:00:37 +02:00
Clifford Wolf 452d4bf741 Added support for "dfflibmap -liberty +/..." 2015-09-18 11:55:57 +02:00
Clifford Wolf 51e1295d79 Added detection of "mux inverter" chains in opt_const 2015-09-18 11:55:31 +02:00
Clifford Wolf b7535a6c75 Added $logic_not handling to fsm_detect 2015-09-18 10:46:50 +02:00
Clifford Wolf c89ceee219 Added $finish and $display to README 2015-09-18 10:01:08 +02:00
Clifford Wolf 7a230d3a8d Merge branch 'feat-finish-disp' 2015-09-18 09:54:49 +02:00
Clifford Wolf 9db05d17fe Added AST_INITIAL checks for $finish and $display 2015-09-18 09:50:57 +02:00
Andrew Zonenberg 7141f65533 Initial implementation of $display() 2015-09-18 09:36:46 +02:00
Andrew Zonenberg e446e651cb Initial implementation of $finish() 2015-09-18 09:30:25 +02:00
Clifford Wolf d9cecabb87 Fixed copy&paste typo in synth_greenpak4 2015-09-16 09:39:31 +02:00