Commit Graph

42 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka 3209c0762a intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff.
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
Claire Wolf cef607c8b7 Add log_experimental() and experimental() API and "yosys -x"
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
whitequark f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
Eddie Hung 79448f9be0 Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
Eddie Hung aa6d06c1b5 Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
This reverts commit 6008bb7002.
2019-12-30 13:28:29 -08:00
Dan Ravensloft 85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
Dan Ravensloft eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Ben Widawsky 7de098ad45 techlibs/intel: Clean up Makefile
Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-08-05 11:22:11 -07:00
Clifford Wolf eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Dan Ravensloft 49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Dan Ravensloft 67b4ce06e0 intel: Map M9K BRAM only on families that have it
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
2019-07-23 18:11:11 +01:00
David Shah 9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups
Assorted synth_intel cleanups from @bwidawsk
2019-07-18 19:04:28 +01:00
Dan Ravensloft 0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
Dan Ravensloft 50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Ben Widawsky 999811572a intel_synth: Fix help message
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:25 +01:00
Ben Widawsky f950a7a75d intel_synth: Small code cleanup to remove if ladder
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:12 +01:00
Ben Widawsky 809b94a67b intel_synth: Make family explicit and match
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:03 +01:00
Ben Widawsky 060e77c09b intel_synth: Minor code cleanups
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:05:54 +01:00
Dan Ravensloft c78ab8ebc5 synth_intel: rename for consistency with #1184
Also fix a typo in the help message.
2019-07-18 16:46:21 +01:00
Dan Ravensloft 4f798cda9d synth_intel: Warn about untested Quartus backend 2019-07-07 19:26:31 +01:00
Ben Widawsky 05d8cc4567 Fix formatting for synth_intel.cc
This is realized through the recently added .clang-format file.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-09 08:40:05 -07:00
Diego 643ae9bfc5 Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
Larry Doolittle e2fc18f27b Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
Miodrag Milanovic 3b17c9018a Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Diego H 819ca73096 Changes in GoWin synth commands and ALU primitive support 2018-12-03 20:08:35 -06:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes.
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf b4c1d3084f Add "synth_intel --noiopads"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-30 13:02:56 +02:00
c60k28 efed2420d6 Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device 2018-03-31 22:48:47 -06:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
dh73 3fd1d61e2a Initial Cyclone 10 support 2017-11-08 22:45:21 -06:00
Larry Doolittle 50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73 4718e65763 Tested and working altsyncarm without init files 2017-10-01 19:59:45 -05:00
dh73 cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00