yosys

Commit Graph

Author	SHA1	Message	Date
Eddie Hung	864bff14f1	Revert "Special abc9_clock wire to contain only clock signal" This reverts commit `6a2eb5d8f9`.	2019-12-05 11:11:53 -08:00
Eddie Hung	0d248dd7ba	Missing wire declaration	2019-12-04 23:04:40 -08:00
Eddie Hung	19bc429482	abc9_map.v to transform INIT=1 to INIT=0	2019-12-04 21:36:41 -08:00
Eddie Hung	b43986c5a1	output reg Q -> output Q to suppress warning	2019-12-04 16:34:34 -08:00
Eddie Hung	31ef4cc704	abc9_map.v to do `zinit' and make INIT = 1'b0	2019-12-04 16:11:02 -08:00
Eddie Hung	a181ff66d3	Add abc9_init wire, attach to abc9_flop cell	2019-12-03 18:47:09 -08:00
Eddie Hung	f98aa1c13f	Revert "Add INIT value to abc9_control" This reverts commit `19bfb41958`.	2019-12-03 15:40:44 -08:00
Eddie Hung	19bfb41958	Add INIT value to abc9_control	2019-12-02 14:17:06 -08:00
Eddie Hung	6a2eb5d8f9	Special abc9_clock wire to contain only clock signal	2019-11-25 12:36:13 -08:00
Eddie Hung	5a30e3ac3b	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	2019-11-21 16:15:25 -08:00
Eddie Hung	df63d75ff3	Fix INIT values	2019-11-20 11:26:59 -08:00
Eddie Hung	344619079d	Do not drop async control signals in abc_map.v	2019-11-19 16:57:07 -08:00
Eddie Hung	4f0818275f	Cleanup	2019-10-07 15:58:55 -07:00
Eddie Hung	b2e34f932a	Rename $currQ to $abc9_currQ	2019-10-07 15:31:43 -07:00
Eddie Hung	bae3d8705d	Update comments in abc9_map.v	2019-10-07 12:54:45 -07:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	7959e9d6b2	Fix merge issues	2019-10-04 17:21:14 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00

19 Commits