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11295 Commits

Author SHA1 Message Date
Aki Van Ness ad81cff823
Changed the Makefile to have an explicit `CXXSTD` parameter which allows for the setting of other C++ standards, the default is `c++11` 2021-10-31 20:07:30 -04:00
Claire Xen dd06d23649
Merge pull request #3066 from YosysHQ/claire/verific_gclk 
Fix verific gclk handling for async-load FFs
 2021-10-31 18:04:54 +01:00
Claire Xenia Wolf 83118bfb9e Fix verific gclk handling for async-load FFs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-31 17:12:29 +01:00
github-actions[bot] dcb7096b5a Bump version 2021-10-30 00:51:07 +00:00
Miodrag Milanovic c0edfa8788 Add missing items in CHANGELOG 2021-10-29 13:31:41 +02:00
Miodrag Milanovic 55f07fe56f Update command reference part of manual 2021-10-29 13:10:50 +02:00
github-actions[bot] 5f00bf2d7d Bump version 2021-10-28 00:52:35 +00:00
Miodrag Milanović 19c2d6e15d
Merge pull request #3063 from YosysHQ/micko/verific_aldff 
Enable async load dff emit by default in Verific
 2021-10-27 17:20:31 +02:00
Marcelina Kościelnicka e14302a3ea ecp5: Add support for mapping aldff. 2021-10-27 16:18:05 +02:00
Miodrag Milanovic f7cc388bb5 Enable async load dff emit by default in Verific 2021-10-27 15:56:56 +02:00
Miodrag Milanovic 32673edfea Revert "Compile option for enabling async load verific support" 
This reverts commit b8624ad2ae.
 2021-10-27 15:55:43 +02:00
Marcelina Kościelnicka 8d881826eb proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka 0b31cb598e dfflegalize: Add tests for aldff lowering. 2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka 54c79af64f dfflegalize: Add tests targetting aldff. 2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
github-actions[bot] bdf153d06c Bump version 2021-10-27 00:51:44 +00:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule 
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
 2021-10-25 18:25:50 -07:00
github-actions[bot] ee230f2bb9 Bump version 2021-10-26 00:51:59 +00:00
Miodrag Milanovic b8624ad2ae Compile option for enabling async load verific support 2021-10-25 09:04:43 +02:00
github-actions[bot] 52ba31b1c0 Bump version 2021-10-22 01:00:39 +00:00
Marcelina Kościelnicka 5cebf6a8ef Change implicit conversions from bool to Sig* to explicit. 
Also fixes some completely broken code in extract_reduce.
 2021-10-21 20:20:31 +02:00
Claire Xen 51d42cc917
Merge pull request #3057 from YosysHQ/claire/verific_latches 
Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
 2021-10-21 13:00:53 +02:00
Claire Xenia Wolf 90b440f870 Fix verific.cc PRIM_DLATCH handling 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-21 12:13:35 +02:00
Claire Xenia Wolf 16a177560f Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-21 05:42:47 +02:00
Marcelina Kościelnicka e64456f920 extract_reduce: Refactor and fix input signal construction. 
Fixes #3047.
 2021-10-21 04:10:01 +02:00
github-actions[bot] a0e9d9fef9 Bump version 2021-10-21 00:59:29 +00:00
Miodrag Milanovic bf79ff5927 If verific have vhdl lib it is required by other libs 2021-10-20 13:08:08 +02:00
Miodrag Milanovic 150ce305f9 Forgot to remove from main list 2021-10-20 12:37:22 +02:00
Miodrag Milanovic 17269ae59b Option to disable verific VHDL support 2021-10-20 10:02:58 +02:00
github-actions[bot] 69b2b13ddd Bump version 2021-10-20 00:56:49 +00:00
Claire Xenia Wolf fe9689c136 Fixed Verific parser error in ice40 cell library 
non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
 2021-10-19 12:33:18 +02:00
Miodrag Milanović affed103e0
Merge pull request #3045 from galibert/master 
CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose
 2021-10-19 11:23:57 +02:00
Claire Xenia Wolf 83887495b8 Fixes in vcdcd.pl for newer Perl versions 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-19 10:56:43 +02:00
github-actions[bot] a15b01a777 Bump version 2021-10-18 00:56:23 +00:00
Paul Annesley 3efc14f5ad dfflegalize: remove redundant check for initialized dlatch 
This if condition is repeated verbatim, and I can't imagine a legitimate
way the inputs could change in between. I imagine it's a copy/paste
mistake.
 2021-10-17 22:10:37 +02:00
Olivier Galibert 6e78a80ff9 CycloneV: Add (passthrough) support for cyclonev_oscillator 2021-10-17 20:00:03 +02:00
Olivier Galibert 6253d4ec9e CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose 2021-10-17 10:39:13 +02:00
github-actions[bot] 0dd42d406d Bump version 2021-10-16 00:58:22 +00:00
Claire Xen 92ecfb2b36
Merge pull request #3044 from YosysHQ/micko/verific_bufif1 
Support PRIM_BUFIF1 primitive, fixes #2981
 2021-10-15 16:43:25 +02:00
Miodrag Milanovic 1aa6896966 Support PRIM_BUFIF1 primitive 2021-10-14 13:04:32 +02:00
github-actions[bot] a0f5ba8501 Bump version 2021-10-12 00:57:44 +00:00
Claire Xen 2d3c79458d
Merge pull request #3039 from YosysHQ/claire/verific_aldff 
Add support for $aldff flip-flops to verific importer
 2021-10-11 10:01:56 +02:00
Claire Xenia Wolf c8074769b0 Add Verific adffe/dffsre/aldffe FIXMEs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-11 10:00:20 +02:00
Claire Xen d5cc3a1c72
Merge pull request #3040 from YosysHQ/micko/split_module_ports 
Split module ports, 20 per line
 2021-10-11 09:56:05 +02:00
Claire Xen c15b99c0de
Merge pull request #3041 from YosysHQ/mmicko/module_attr 
Import module attributes from Verific
 2021-10-11 09:54:28 +02:00
Miodrag Milanovic 93fbc9fba4 Import module attributes from Verific 2021-10-10 10:01:45 +02:00
Miodrag Milanovic ff8e999a71 Split module ports, 20 per line 2021-10-09 13:40:55 +02:00
github-actions[bot] d8f6d7b18d Bump version 2021-10-09 00:51:28 +00:00
Claire Xenia Wolf 34f1df8435 Fixes and add comments for open FIXME items 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 17:24:45 +02:00