mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3041 from YosysHQ/mmicko/module_attr
Import module attributes from Verific
This commit is contained in:
commit
c15b99c0de
|
@ -917,6 +917,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
|
|||
} else {
|
||||
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
|
||||
}
|
||||
import_attributes(module->attributes, nl, nl);
|
||||
|
||||
SetIter si;
|
||||
MapIter mi, mi2;
|
||||
|
|
Loading…
Reference in New Issue