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Merge pull request #3063 from YosysHQ/micko/verific_aldff 

Enable async load dff emit by default in Verific
This commit is contained in:
Miodrag Milanović 2021-10-27 17:20:31 +02:00 committed by GitHub
parent e14302a3ea f7cc388bb5
commit 19c2d6e15d
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 1 additions and 8 deletions
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4
Makefile
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@ -20,7 +20,6 @@ ENABLE_GHDL := 0
ENABLE_VERIFIC := 0
DISABLE_VERIFIC_EXTENSIONS := 0
DISABLE_VERIFIC_VHDL := 0
ENABLE_VERIFIC_ASYNC_LOAD := 0
ENABLE_COVER := 1
ENABLE_LIBYOSYS := 0
ENABLE_PROTOBUF := 0
@ -502,9 +501,6 @@ endif
ifeq ($(ENABLE_VERIFIC),1)
VERIFIC_DIR ?= /usr/local/src/verific_lib
VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
ifeq ($(ENABLE_VERIFIC_ASYNC_LOAD),1)
CXXFLAGS += -DVERIFIC_ASYNC_LOAD
endif
ifneq ($(DISABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT

5
frontends/verific/verific.cc
View File

@ -2474,11 +2474,8 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("db_preserve_user_nets", 1);
RuntimeFlags::SetVar("db_allow_external_nets", 1);
RuntimeFlags::SetVar("db_infer_wide_operators", 1);
#ifdef VERIFIC_ASYNC_LOAD
RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
#else
RuntimeFlags::SetVar("db_infer_set_reset_registers", 1);
#endif
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);