whitequark
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ba099bfe9b
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synth_{ice40,ecp5}: more sensible pass label naming.
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2019-07-16 20:41:51 +00:00 |
Eddie Hung
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7a58ee78dc
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gen_lut to return correctly sized LUT mask
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2019-07-16 12:45:29 -07:00 |
Eddie Hung
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ba8ccbdea8
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Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
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2019-07-16 08:52:14 -07:00 |
Eddie Hung
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5fb27c071b
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$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
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2019-07-15 12:03:51 -07:00 |
Eddie Hung
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d032198fac
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ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
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2019-07-13 01:11:00 -07:00 |
Clifford Wolf
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463f710066
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Merge pull request #1183 from whitequark/ice40-always-relut
synth_ice40: switch -relut to be always on
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2019-07-12 10:48:00 +02:00 |
Eddie Hung
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7a912f22b2
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Use Const::from_string() not its constructor...
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2019-07-12 01:32:10 -07:00 |
Eddie Hung
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28274dfb09
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Off by one
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2019-07-12 01:17:53 -07:00 |
Eddie Hung
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e0e5d7d68e
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Fix spacing
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2019-07-12 01:15:22 -07:00 |
Eddie Hung
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4de03bd5e6
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Remove double push
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2019-07-12 01:08:48 -07:00 |
Eddie Hung
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62ac5ebd02
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Map to and from this box if -abc9
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2019-07-12 00:53:01 -07:00 |
Eddie Hung
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0f5bddcd79
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ice40_opt to handle this box and opt back to SB_LUT4
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2019-07-12 00:52:31 -07:00 |
Eddie Hung
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a79ff2501e
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Add new box to cells_sim.v
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2019-07-12 00:52:19 -07:00 |
Eddie Hung
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c6e16e1334
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_ABC macro will map and unmap to this new box
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2019-07-12 00:51:37 -07:00 |
Eddie Hung
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fc3d74616f
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Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
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2019-07-12 00:50:42 -07:00 |
whitequark
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b700a4b1c5
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synth_ice40: switch -relut to be always on.
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2019-07-11 20:18:41 +00:00 |
whitequark
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a8c5f7f41e
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synth_ice40: fix help text typo. NFC.
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2019-07-11 20:18:41 +00:00 |
Eddie Hung
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19c1c3cfa3
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Merge pull request #1182 from koriakin/xc6s-bram
synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 12:55:35 -07:00 |
Marcin Kościelnicki
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a9efacd01d
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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
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2019-07-11 21:13:12 +02:00 |
Marcin Kościelnicki
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ce250b341c
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
Eddie Hung
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bb2144ae73
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Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Error out if -abc9 and -retime specified
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2019-07-10 14:38:13 -07:00 |
Eddie Hung
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2f990a7319
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Merge pull request #1148 from YosysHQ/xc7mux
synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
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2019-07-10 14:38:00 -07:00 |
Eddie Hung
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6bbd286e03
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Error out if -abc9 and -retime specified
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2019-07-10 12:47:48 -07:00 |
Eddie Hung
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58bb84e5b2
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Add some spacing
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2019-07-10 12:32:33 -07:00 |
Eddie Hung
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521971e32e
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Add some ASCII art explaining mux decomposition
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2019-07-10 12:20:04 -07:00 |
Eddie Hung
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e573d024a2
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Call muxpack and pmux2shiftx before cmp2lut
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2019-07-09 21:26:38 -07:00 |
Eddie Hung
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c55530b901
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Restore opt_clean back to original place
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2019-07-09 14:29:58 -07:00 |
Eddie Hung
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5b48b18d29
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Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
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2019-07-09 14:28:54 -07:00 |
David Shah
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27b27b8781
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synth_ecp5: Fix typo in copyright header
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-09 22:26:10 +01:00 |
Eddie Hung
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b1a048a703
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Extend using A[1] to preserve don't care
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2019-07-09 12:35:41 -07:00 |
Eddie Hung
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93522b0ae1
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Extend during mux decomposition with 1'bx
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2019-07-09 10:59:37 -07:00 |
Eddie Hung
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c864995343
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Fix typo and comments
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2019-07-09 10:38:07 -07:00 |
Eddie Hung
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c91cb73562
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-07-09 10:22:49 -07:00 |
Eddie Hung
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c68b909210
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synth_xilinx to call commands of synth -coarse directly
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2019-07-09 10:21:54 -07:00 |
Eddie Hung
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737340327f
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Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
This reverts commit 7f964859ec .
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2019-07-09 10:15:02 -07:00 |
Eddie Hung
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713337255e
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Revert "Add "synth -keepdc" option"
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2019-07-09 10:14:23 -07:00 |
Eddie Hung
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bc84f7dd10
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Fix spacing
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2019-07-09 09:22:12 -07:00 |
Eddie Hung
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667199d460
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Fix spacing
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2019-07-09 09:16:00 -07:00 |
Clifford Wolf
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a429aedc0f
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Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Cleanup synth_xilinx SRL inference, make more consistent
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2019-07-09 16:49:08 +02:00 |
Eddie Hung
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6951e32070
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Decompose mux inputs in delay-orientated (rather than area) fashion
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2019-07-08 23:51:13 -07:00 |
Eddie Hung
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45da3ada7b
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Do not call opt -mux_undef (part of -full) before muxcover
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2019-07-08 23:49:16 -07:00 |
Eddie Hung
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d4ab43d940
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Add one more comment
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2019-07-08 23:05:48 -07:00 |
Eddie Hung
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939a225f92
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Less thinking
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2019-07-08 23:02:57 -07:00 |
Eddie Hung
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de40453553
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Reword
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2019-07-08 22:56:19 -07:00 |
Eddie Hung
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7f8c420cf7
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Merge pull request #1166 from YosysHQ/eddie/synth_keepdc
Add "synth -keepdc" option
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2019-07-08 21:43:16 -07:00 |
Eddie Hung
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7f964859ec
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synth_xilinx to call "synth -run coarse" with "-keepdc"
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2019-07-08 19:23:24 -07:00 |
Eddie Hung
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9ac078be6f
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Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux
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2019-07-08 19:21:53 -07:00 |
Eddie Hung
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dd9771cbcd
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Add synth -keepdc option
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2019-07-08 19:14:54 -07:00 |
Eddie Hung
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3f86407cc3
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Map $__XILINX_SHIFTX in a more balanced manner
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2019-07-08 17:06:35 -07:00 |
Eddie Hung
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78914e2e0e
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Capitalisation
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2019-07-08 17:06:22 -07:00 |
Eddie Hung
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baf47e496f
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Add synth_xilinx -widemux recommended value
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2019-07-08 17:04:39 -07:00 |
Eddie Hung
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895ca50173
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Fixes for 2:1 muxes
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2019-07-08 12:03:38 -07:00 |
Eddie Hung
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0944acf3af
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synth_xilinx -widemux=2 is minimum now
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2019-07-08 11:29:21 -07:00 |
Eddie Hung
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dbe1326573
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Parametric muxcover costs as per @daveshah1
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2019-07-08 11:08:20 -07:00 |
Eddie Hung
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c58998a7d2
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atoi -> stoi as per @daveshah1
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2019-07-08 10:48:10 -07:00 |
Dan Ravensloft
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4f798cda9d
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synth_intel: Warn about untested Quartus backend
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2019-07-07 19:26:31 +01:00 |
Eddie Hung
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810f8c5dbd
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Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
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2019-07-02 09:21:02 -07:00 |
Eddie Hung
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2ea6083b7e
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Fix $__XILINX_MUXF78 box timing
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2019-07-01 14:04:06 -07:00 |
Eddie Hung
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09ac274716
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Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
This reverts commit a9a140aa6c .
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2019-07-01 14:01:09 -07:00 |
Eddie Hung
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a9a140aa6c
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Fix broken MUXFx box, use MUXF7x2 box instead
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2019-07-01 13:36:27 -07:00 |
Eddie Hung
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85f1c2dcbe
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Cleanup SRL inference/make more consistent
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2019-06-29 21:42:20 -07:00 |
Eddie Hung
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62ba724ccb
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-29 19:39:27 -07:00 |
Eddie Hung
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dd8d264bf5
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install *_nowide.lut files
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2019-06-29 19:37:04 -07:00 |
Eddie Hung
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728839d6ca
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Remove peepopt call in synth_xilinx since already in synth -run coarse
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2019-06-28 12:53:38 -07:00 |
Eddie Hung
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ea0f7c9be9
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Restore $__XILINX_MUXF78 const optimisation
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2019-06-28 12:12:41 -07:00 |
Eddie Hung
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a193bf27c9
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Clean up trimming leading 1'bx in A during techmappnig
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2019-06-28 12:03:43 -07:00 |
Eddie Hung
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cf020befeb
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Fix CARRY4 abc_box_id
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2019-06-28 11:28:50 -07:00 |
Eddie Hung
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4ef26d4755
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-28 11:09:42 -07:00 |
Eddie Hung
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03705f69f4
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Update synth_ice40 -device doc to be relevant for -abc9 only
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2019-06-28 09:49:01 -07:00 |
Eddie Hung
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3f87575cb6
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Disable boxing of ECP5 dist RAM due to regression
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2019-06-28 09:46:36 -07:00 |
Eddie Hung
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0318860b93
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Add write address to abc_scc_break of ECP5 dist RAM
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2019-06-28 09:45:48 -07:00 |
Eddie Hung
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b9ddee0c87
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Fix DO4 typo
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2019-06-28 09:45:40 -07:00 |
Eddie Hung
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00f63d82ce
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Reduce diff with upstream
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2019-06-27 16:13:22 -07:00 |
Eddie Hung
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af8a5ae5fe
|
Extraneous newline
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2019-06-27 16:12:20 -07:00 |
Eddie Hung
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4daa746797
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Remove noise from ice40/cells_sim.v
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2019-06-27 16:11:39 -07:00 |
Eddie Hung
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9398921af1
|
Refactor for one "abc_carry" attribute on module
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2019-06-27 16:07:14 -07:00 |
Eddie Hung
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312c03e4ca
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Remove redundant doc
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2019-06-27 15:28:55 -07:00 |
Eddie Hung
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4d00e27ed7
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Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-27 11:23:30 -07:00 |
Eddie Hung
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1237a4c116
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Add warning if synth_xilinx -abc9 with family != xc7
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2019-06-27 11:22:49 -07:00 |
Eddie Hung
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6c256b8cda
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
Eddie Hung
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593e4a30bb
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MUXF78 -> $__MUXF78 to indicate internal
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2019-06-26 20:09:28 -07:00 |
Eddie Hung
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dbb8c8caaa
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Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-26 20:07:31 -07:00 |
Eddie Hung
|
4de25a1949
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Add WE to ECP5 dist RAM's abc_scc_break too
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2019-06-26 20:02:19 -07:00 |
Eddie Hung
|
a7a88109f5
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Update comment on boxes
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2019-06-26 20:00:15 -07:00 |
Eddie Hung
|
b7bef15b16
|
Add "WE" to dist RAM's abc_scc_break
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2019-06-26 19:58:09 -07:00 |
Eddie Hung
|
b9ff0503f3
|
synth_xilinx's muxcover call to be very conservative -- -nodecode
|
2019-06-26 17:57:10 -07:00 |
Eddie Hung
|
f0a1726a1a
|
Accidentally removed "simplemap $mux"
|
2019-06-26 17:48:49 -07:00 |
Eddie Hung
|
2b104ed6c8
|
Replace with <internal options>
|
2019-06-26 17:42:50 -07:00 |
Eddie Hung
|
cae69a3edd
|
Rework help_mode for synth_xilinx -widemux
|
2019-06-26 17:41:21 -07:00 |
Eddie Hung
|
5f807a7a5b
|
Return to upstream synth_xilinx with opt -full and wreduce
|
2019-06-26 16:25:48 -07:00 |
Eddie Hung
|
812469aaa3
|
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
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2019-06-26 14:48:35 -07:00 |
Eddie Hung
|
c762be5930
|
Instead of blocking wreduce on $mux, use -keepdc instead #1132
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2019-06-26 11:48:35 -07:00 |
Eddie Hung
|
8d8261c71f
|
Do not call opt with -full before muxcover
|
2019-06-26 11:38:28 -07:00 |
Eddie Hung
|
80de03a7a6
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-26 11:24:39 -07:00 |
Eddie Hung
|
4d0014d1b1
|
Cleanup abc_box_id
|
2019-06-26 11:23:57 -07:00 |
Eddie Hung
|
612083a807
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-26 10:33:54 -07:00 |
Eddie Hung
|
5e1b8d458b
|
Remove unused var
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2019-06-26 10:33:07 -07:00 |
Eddie Hung
|
988e6163ab
|
Add _nowide variants of LUT libraries in -nowidelut flows
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2019-06-26 10:23:29 -07:00 |
Eddie Hung
|
741ebba70a
|
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-06-26 10:10:16 -07:00 |
Eddie Hung
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799b18263f
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Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26 10:04:01 -07:00 |