Miodrag Milanović
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a95e5d505b
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Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id
add argument for printing cell names in yosys-smtbmc
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2022-03-04 16:39:12 +01:00 |
Miodrag Milanović
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13655ddccf
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Merge pull request #3206 from YosysHQ/micko/quote_remove
Remove quotes if any from attribute
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2022-03-04 16:39:01 +01:00 |
Miodrag Milanović
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c3124023e4
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Merge pull request #3207 from nakengelhardt/json_escape_quotes
fix handling of escaped chars in json backend and frontend (mostly)
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2022-03-04 13:57:32 +01:00 |
Miodrag Milanovic
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7be7f5e02e
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Next dev cycle
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2022-03-04 11:37:18 +01:00 |
Miodrag Milanovic
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07a43689d8
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Release version 0.15
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2022-03-04 11:36:03 +01:00 |
Miodrag Milanovic
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66ba5ed7a5
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Update ABC
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2022-03-04 11:32:15 +01:00 |
Miodrag Milanovic
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a7090e9711
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Update documentation
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2022-03-04 10:56:33 +01:00 |
Miodrag Milanović
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9581b9adac
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Merge pull request #3219 from YosysHQ/micko/quick_vcd
VCD reader support by using external tool
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2022-03-04 10:42:14 +01:00 |
Miodrag Milanović
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d1fbe738a7
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Merge pull request #3220 from YosysHQ/claire/simstuff
Add writing of aiw files to "sim" command
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2022-03-04 10:41:02 +01:00 |
github-actions[bot]
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e768f7552c
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Bump version
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2022-03-03 01:08:21 +00:00 |
Miodrag Milanovic
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59983eda17
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Add option to ignore X only signals in output
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2022-03-02 16:02:13 +01:00 |
Miodrag Milanovic
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48b56a4f7f
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Write simulation files after simulation is performed
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2022-03-02 15:23:07 +01:00 |
Miodrag Milanovic
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3818e1160d
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Update CHANGELOG
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2022-03-02 14:26:15 +01:00 |
Claire Xen
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2ca69e1b88
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Merge pull request #3224 from YosysHQ/micko/refactor
Micko/refactor
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2022-03-02 13:52:18 +01:00 |
Miodrag Milanovic
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28bc88a57e
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Cleanup
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2022-03-02 09:39:22 +01:00 |
github-actions[bot]
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4a38d15f0d
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Bump version
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2022-03-01 01:12:24 +00:00 |
Miodrag Milanovic
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94505395a9
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Refactor sim output writers
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2022-02-28 18:22:39 +01:00 |
Miodrag Milanovic
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dfd4c81eac
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Quick fix
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2022-02-28 11:40:06 +01:00 |
Claire Xenia Wolf
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56b968f61c
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Add writing of aiw files to "sim" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2022-02-28 10:50:08 +01:00 |
Claire Xenia Wolf
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1fd3a642c9
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Hotfix in AIGER witness reader state machine
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2022-02-28 10:41:44 +01:00 |
Miodrag Milanovic
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8be09b5b24
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VCD reader support by using external tool
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2022-02-28 09:09:07 +01:00 |
Miodrag Milanović
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ec4af6af2f
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Merge pull request #3216 from YosysHQ/claire/simstuff
Co-simulation improvements and fixes
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2022-02-28 08:19:54 +01:00 |
Miodrag Milanovic
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9571acc0bf
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Support extended aiw format
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2022-02-27 16:37:40 +01:00 |
Miodrag Milanovic
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fca168797e
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Fix for last clock edge data
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2022-02-25 16:15:32 +01:00 |
Claire Xenia Wolf
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ca261d3c28
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Experimental sim changes
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2022-02-25 16:02:06 +01:00 |
github-actions[bot]
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08c771078f
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Bump version
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2022-02-25 01:04:22 +00:00 |
YRabbit
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22d9bbb308
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gowin: Remove unnecessary attributes
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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2022-02-24 05:38:33 +01:00 |
YRabbit
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9b3cd4f0d8
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gowin: Add support for true differential output
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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2022-02-24 05:38:33 +01:00 |
Anton Blanchard
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89300b2dca
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abc: Fix {I} and {P} substitution
We were searching for {D} after the first match of {I} or {P}.
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2022-02-23 18:54:28 +11:00 |
N. Engelhardt
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dc739362c7
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print cell name for properties in yosys-smtbmc
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2022-02-22 17:00:10 +01:00 |
Claire Xen
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a41c1df76f
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Merge pull request #3211 from YosysHQ/micko/witness
Add support for AIGER witness files in "sim" command
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2022-02-22 16:22:06 +01:00 |
Claire Xen
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ac294ed419
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Merge pull request #3197 from YosysHQ/claire/smtbmcfix
Add a bit of flexibilty re AIG witness trace length to smtbmc.py
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2022-02-22 15:26:22 +01:00 |
R
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2d3a337795
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json: Add help message for `signed` field
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2022-02-21 21:59:25 -08:00 |
github-actions[bot]
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286caa09bd
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Bump version
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2022-02-22 00:59:35 +00:00 |
Miodrag Milanović
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d0b72e75d9
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Merge pull request #3203 from YosysHQ/micko/sim_ff
Simulation for various FF types
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2022-02-21 17:57:44 +01:00 |
Marcelina Kościelnicka
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d0f4d0b153
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ecp5: Do not use specify in generate in cells_sim.v.
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2022-02-21 17:52:31 +01:00 |
Miodrag Milanovic
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fd3f08753a
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Fix handling of ce_over_srst
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2022-02-21 16:36:12 +01:00 |
N. Engelhardt
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8fd1b06249
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fix handling of escaped chars in json backend and frontend
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2022-02-18 17:13:09 +01:00 |
Claire Xenia Wolf
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1aa9ad25d0
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Fix cycle 0 in aiger witness co-simulation
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2022-02-18 16:27:41 +01:00 |
Miodrag Milanovic
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5f918803de
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Changed error message
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2022-02-18 15:06:49 +01:00 |
Miodrag Milanovic
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41754b4207
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Added AIGER witness file co simulation
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2022-02-18 15:04:02 +01:00 |
Miodrag Milanovic
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13a5c28459
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simplify logic of handling flip-flops and latches
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2022-02-18 09:17:36 +01:00 |
Miodrag Milanovic
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61752b255f
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Review cleanup
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2022-02-17 17:18:36 +01:00 |
Miodrag Milanovic
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29293a57bb
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Remove quotes if any from attribute
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2022-02-16 19:10:13 +01:00 |
Miodrag Milanovic
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21baf48e04
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test dlatchsr and adlatch
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2022-02-16 13:58:51 +01:00 |
Miodrag Milanovic
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271ac28b41
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Added test cases
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2022-02-16 13:27:59 +01:00 |
Miodrag Milanovic
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fb22d7cdc4
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Add support for various ff/latch cells simulation
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2022-02-16 13:27:59 +01:00 |
github-actions[bot]
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1586000048
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Bump version
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2022-02-16 01:01:23 +00:00 |
Miodrag Milanović
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c9a32c0d92
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Merge pull request #3204 from YosysHQ/claire/update-abc
Bump ABC version
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2022-02-15 20:51:54 +01:00 |
Miodrag Milanovic
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3bae2705fc
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Bump ABC version
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2022-02-15 18:44:05 +01:00 |