mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3220 from YosysHQ/claire/simstuff
Add writing of aiw files to "sim" command
This commit is contained in:
Miodrag Milanović
GitHub
commit
d1fbe738a7
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@ -65,6 +65,15 @@ static double stringToTime(std::string str)
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return value * pow(10.0, g_units.at(endptr));
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}
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struct SimWorker;
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struct OutputWriter
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{
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OutputWriter(SimWorker *w) { worker = w;};
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virtual ~OutputWriter() {};
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virtual void write(std::map<int, bool> &use_signal) = 0;
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SimWorker *worker;
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};
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struct SimShared
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{
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bool debug = false;
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@ -77,6 +86,9 @@ struct SimShared
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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std::vector<std::unique_ptr<OutputWriter>> outputfiles;
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std::vector<std::pair<int,std::map<int,Const>>> output_data;
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bool ignore_x = false;
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};
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void zinit(State &v)
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@ -140,8 +152,7 @@ struct SimInstance
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std::vector<Mem> memories;
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dict<Wire*, pair<int, Const>> vcd_database;
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dict<Wire*, pair<fstHandle, Const>> fst_database;
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dict<Wire*, pair<int, Const>> signal_database;
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dict<Wire*, fstHandle> fst_handles;
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SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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@ -685,28 +696,39 @@ struct SimInstance
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it.second->writeback(wbmods);
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}
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void write_vcd_header(std::ofstream &f, int &id)
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void register_signals(int &id)
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{
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f << stringf("$scope module %s $end\n", log_id(name()));
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for (auto wire : module->wires())
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{
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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f << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
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vcd_database[wire] = make_pair(id++, Const());
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signal_database[wire] = make_pair(id, Const());
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id++;
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}
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for (auto child : children)
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child.second->write_vcd_header(f, id);
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f << stringf("$upscope $end\n");
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child.second->register_signals(id);
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}
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void write_vcd_step(std::ofstream &f)
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void write_output_header(std::function<void(IdString)> enter_scope, std::function<void()> exit_scope, std::function<void(Wire*, int)> register_signal)
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{
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for (auto &it : vcd_database)
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enter_scope(name());
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for (auto signal : signal_database)
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{
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register_signal(signal.first, signal.second.first);
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}
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for (auto child : children)
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child.second->write_output_header(enter_scope, exit_scope, register_signal);
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exit_scope();
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}
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void register_output_step_values(std::map<int,Const> *data)
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{
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for (auto &it : signal_database)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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@ -716,69 +738,11 @@ struct SimInstance
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continue;
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it.second.second = value;
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f << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: f << "0"; break;
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case State::S1: f << "1"; break;
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case State::Sx: f << "x"; break;
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default: f << "z";
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}
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}
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f << stringf(" n%d\n", id);
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data->emplace(id, value);
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}
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for (auto child : children)
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child.second->write_vcd_step(f);
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}
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void write_fst_header(struct fstContext *f)
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{
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fstWriterSetScope(f, FST_ST_VCD_MODULE, stringf("%s",log_id(name())).c_str(), nullptr);
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for (auto wire : module->wires())
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{
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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fstHandle id = fstWriterCreateVar(f, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
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stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
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fst_database[wire] = make_pair(id, Const());
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}
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for (auto child : children)
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child.second->write_fst_header(f);
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fstWriterSetUpscope(f);
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}
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void write_fst_step(struct fstContext *f)
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{
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for (auto &it : fst_database)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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fstHandle id = it.second.first;
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if (it.second.second == value)
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continue;
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it.second.second = value;
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std::stringstream ss;
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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}
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}
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fstWriterEmitValueChange(f, id, ss.str().c_str());
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}
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for (auto child : children)
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child.second->write_fst_step(f);
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child.second->register_output_step_values(data);
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}
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void setInitState()
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@ -857,8 +821,6 @@ struct SimInstance
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struct SimWorker : SimShared
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{
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SimInstance *top = nullptr;
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std::ofstream vcdfile;
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struct fstContext *fstfile = nullptr;
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pool<IdString> clock, clockn, reset, resetn;
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std::string timescale;
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std::string sim_filename;
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@ -867,75 +829,41 @@ struct SimWorker : SimShared
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~SimWorker()
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{
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outputfiles.clear();
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delete top;
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}
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void write_vcd_header()
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void register_signals()
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{
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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std::time_t t = std::time(nullptr);
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char mbstr[255];
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if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
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vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
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}
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if (!timescale.empty())
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vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
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int id = 1;
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top->write_vcd_header(vcdfile, id);
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vcdfile << stringf("$enddefinitions $end\n");
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top->register_signals(id);
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}
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void write_vcd_step(int t)
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void register_output_step(int t)
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{
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vcdfile << stringf("#%d\n", t);
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top->write_vcd_step(vcdfile);
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std::map<int,Const> data;
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top->register_output_step_values(&data);
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output_data.emplace_back(t, data);
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}
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void write_fst_header()
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void write_output_files()
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{
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std::time_t t = std::time(nullptr);
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fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
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fstWriterSetVersion(fstfile, yosys_version_str);
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if (!timescale.empty())
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fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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top->write_fst_header(fstfile);
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}
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void write_fst_step(int t)
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{
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fstWriterEmitTimeChange(fstfile, t);
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top->write_fst_step(fstfile);
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}
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void write_output_header()
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{
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if (vcdfile.is_open())
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write_vcd_header();
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if (fstfile)
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write_fst_header();
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}
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void write_output_step(int t)
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{
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if (vcdfile.is_open())
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write_vcd_step(t);
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if (fstfile)
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write_fst_step(t);
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}
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void write_output_end()
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{
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if (fstfile)
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fstWriterClose(fstfile);
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std::map<int, bool> use_signal;
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bool first = ignore_x;
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for(auto& d : output_data)
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{
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if (first) {
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for (auto &data : d.second)
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use_signal[data.first] = !data.second.is_fully_undef();
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first = false;
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} else {
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for (auto &data : d.second)
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use_signal[data.first] = true;
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}
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if (!ignore_x) break;
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}
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for(auto& writer : outputfiles)
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writer->write(use_signal);
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}
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void update()
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@ -977,6 +905,7 @@ struct SimWorker : SimShared
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{
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log_assert(top == nullptr);
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top = new SimInstance(this, scope, topmod);
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register_signals();
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if (debug)
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log("\n===== 0 =====\n");
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@ -991,8 +920,7 @@ struct SimWorker : SimShared
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update();
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write_output_header();
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write_output_step(0);
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register_output_step(0);
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for (int cycle = 0; cycle < numcycles; cycle++)
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{
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@ -1004,7 +932,7 @@ struct SimWorker : SimShared
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set_inports(clockn, State::S1);
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update();
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write_output_step(10*cycle + 5);
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register_output_step(10*cycle + 5);
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 10);
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@ -1020,12 +948,12 @@ struct SimWorker : SimShared
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}
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update();
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write_output_step(10*cycle + 10);
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register_output_step(10*cycle + 10);
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}
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write_output_step(10*numcycles + 2);
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register_output_step(10*numcycles + 2);
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write_output_end();
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write_output_files();
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if (writeback) {
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pool<Module*> wbmods;
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@ -1042,6 +970,7 @@ struct SimWorker : SimShared
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log_error("Scope must be defined for co-simulation.\n");
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top = new SimInstance(this, scope, topmod);
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register_signals();
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std::vector<fstHandle> fst_clock;
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@ -1133,12 +1062,11 @@ struct SimWorker : SimShared
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if (initial) {
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top->setInitState();
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write_output_header();
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initial = false;
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}
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if (did_something)
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update();
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write_output_step(time);
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register_output_step(time);
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bool status = top->checkSignals();
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if (status)
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@ -1154,7 +1082,8 @@ struct SimWorker : SimShared
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} catch(fst_end_of_data_exception) {
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// end of data detected
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}
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write_output_end();
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write_output_files();
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if (writeback) {
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pool<Module*> wbmods;
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@ -1196,6 +1125,8 @@ struct SimWorker : SimShared
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std::string status;
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int cycle = 0;
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top = new SimInstance(this, scope, topmod);
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register_signals();
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while (!f.eof())
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{
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std::string line;
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@ -1207,7 +1138,6 @@ struct SimWorker : SimShared
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state = 2;
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}
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if (state==1 && line[0]!='b' && line[0]!='c') {
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write_output_header();
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// was old format but with 1 bit latch
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top->setState(latches, status);
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state = 3;
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@ -1223,10 +1153,12 @@ struct SimWorker : SimShared
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state = 2;
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break;
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case 2:
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write_output_header();
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top->setState(latches, line);
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state = 3;
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break;
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default:
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log("Simulating cycle %d.\n", cycle);
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top->setState(inputs, line);
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if (cycle) {
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set_inports(clock, State::S1);
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set_inports(clockn, State::S0);
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@ -1236,22 +1168,233 @@ struct SimWorker : SimShared
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set_inports(clockn, State::S1);
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}
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update();
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write_output_step(10*cycle);
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register_output_step(10*cycle);
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if (cycle) {
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set_inports(clock, State::S0);
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set_inports(clockn, State::S1);
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update();
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write_output_step(10*cycle + 5);
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register_output_step(10*cycle + 5);
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}
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cycle++;
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break;
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}
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}
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write_output_step(10*cycle);
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write_output_end();
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register_output_step(10*cycle);
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write_output_files();
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}
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};
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struct VCDWriter : public OutputWriter
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{
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VCDWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
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vcdfile.open(filename.c_str());
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}
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void write(std::map<int, bool> &use_signal) override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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std::time_t t = std::time(nullptr);
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char mbstr[255];
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if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
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vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
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}
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if (!worker->timescale.empty())
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vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str());
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worker->top->write_output_header(
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[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
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[this]() { vcdfile << stringf("$upscope $end\n");},
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[this,use_signal](Wire *wire, int id) { if (use_signal.at(id)) vcdfile << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire)); }
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);
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vcdfile << stringf("$enddefinitions $end\n");
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for(auto& d : worker->output_data)
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{
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vcdfile << stringf("#%d\n", d.first);
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for (auto &data : d.second)
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{
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if (!use_signal.at(data.first)) continue;
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Const value = data.second;
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vcdfile << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: vcdfile << "0"; break;
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case State::S1: vcdfile << "1"; break;
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case State::Sx: vcdfile << "x"; break;
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default: vcdfile << "z";
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}
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}
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vcdfile << stringf(" n%d\n", data.first);
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}
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}
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}
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std::ofstream vcdfile;
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};
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struct FSTWriter : public OutputWriter
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{
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FSTWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
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fstfile = (struct fstContext *)fstWriterCreate(filename.c_str(),1);
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}
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virtual ~FSTWriter()
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{
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fstWriterClose(fstfile);
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}
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void write(std::map<int, bool> &use_signal) override
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{
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if (!fstfile) return;
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std::time_t t = std::time(nullptr);
|
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fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
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fstWriterSetVersion(fstfile, yosys_version_str);
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if (!worker->timescale.empty())
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fstWriterSetTimescaleFromString(fstfile, worker->timescale.c_str());
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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worker->top->write_output_header(
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[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
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[this]() { fstWriterSetUpscope(fstfile); },
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[this,use_signal](Wire *wire, int id) {
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if (!use_signal.at(id)) return;
|
||||
fstHandle fst_id = fstWriterCreateVar(fstfile, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
|
||||
stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
|
||||
|
||||
mapping.emplace(id, fst_id);
|
||||
}
|
||||
);
|
||||
|
||||
for(auto& d : worker->output_data)
|
||||
{
|
||||
fstWriterEmitTimeChange(fstfile, d.first);
|
||||
for (auto &data : d.second)
|
||||
{
|
||||
if (!use_signal.at(data.first)) continue;
|
||||
Const value = data.second;
|
||||
std::stringstream ss;
|
||||
for (int i = GetSize(value)-1; i >= 0; i--) {
|
||||
switch (value[i]) {
|
||||
case State::S0: ss << "0"; break;
|
||||
case State::S1: ss << "1"; break;
|
||||
case State::Sx: ss << "x"; break;
|
||||
default: ss << "z";
|
||||
}
|
||||
}
|
||||
fstWriterEmitValueChange(fstfile, mapping[data.first], ss.str().c_str());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct fstContext *fstfile = nullptr;
|
||||
std::map<int,fstHandle> mapping;
|
||||
};
|
||||
|
||||
struct AIWWriter : public OutputWriter
|
||||
{
|
||||
AIWWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
|
||||
aiwfile.open(filename.c_str());
|
||||
}
|
||||
|
||||
virtual ~AIWWriter()
|
||||
{
|
||||
aiwfile << '.' << '\n';
|
||||
}
|
||||
|
||||
void write(std::map<int, bool> &) override
|
||||
{
|
||||
if (!aiwfile.is_open()) return;
|
||||
std::ifstream mf(worker->map_filename);
|
||||
std::string type, symbol;
|
||||
int variable, index;
|
||||
while (mf >> type >> variable >> index >> symbol) {
|
||||
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
|
||||
Wire *w = worker->top->module->wire(escaped_s);
|
||||
if (!w)
|
||||
log_error("Wire %s not present in module %s\n",log_signal(w),log_id(worker->top->module));
|
||||
if (index < w->start_offset || index > w->start_offset + w->width)
|
||||
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
|
||||
if (type == "input") {
|
||||
aiw_inputs[variable] = SigBit(w,index);
|
||||
} else if (type == "init") {
|
||||
aiw_inits[variable] = SigBit(w,index);
|
||||
} else if (type == "latch") {
|
||||
aiw_latches[variable] = {SigBit(w,index), false};
|
||||
} else if (type == "invlatch") {
|
||||
aiw_latches[variable] = {SigBit(w,index), true};
|
||||
}
|
||||
}
|
||||
|
||||
worker->top->write_output_header(
|
||||
[](IdString) {},
|
||||
[]() {},
|
||||
[this](Wire *wire, int id) { mapping[wire] = id; }
|
||||
);
|
||||
|
||||
std::map<int, Yosys::RTLIL::Const> current;
|
||||
bool first = true;
|
||||
for(auto& d : worker->output_data)
|
||||
{
|
||||
for (auto &data : d.second)
|
||||
{
|
||||
current[data.first] = data.second;
|
||||
}
|
||||
if (first) {
|
||||
for (int i = 0;; i++)
|
||||
{
|
||||
if (aiw_latches.count(i)) {
|
||||
SigBit bit = aiw_latches.at(i).first;
|
||||
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
|
||||
if (v == State::S1)
|
||||
aiwfile << (aiw_latches.at(i).second ? '0' : '1');
|
||||
else
|
||||
aiwfile << (aiw_latches.at(i).second ? '1' : '0');
|
||||
continue;
|
||||
}
|
||||
aiwfile << '\n';
|
||||
break;
|
||||
}
|
||||
first = false;
|
||||
}
|
||||
|
||||
for (int i = 0;; i++)
|
||||
{
|
||||
if (aiw_inputs.count(i)) {
|
||||
SigBit bit = aiw_inputs.at(i);
|
||||
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
|
||||
if (v == State::S1)
|
||||
aiwfile << '1';
|
||||
else
|
||||
aiwfile << '0';
|
||||
continue;
|
||||
}
|
||||
if (aiw_inits.count(i)) {
|
||||
SigBit bit = aiw_inits.at(i);
|
||||
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
|
||||
if (v == State::S1)
|
||||
aiwfile << '1';
|
||||
else
|
||||
aiwfile << '0';
|
||||
continue;
|
||||
}
|
||||
aiwfile << '\n';
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
std::ofstream aiwfile;
|
||||
dict<int, std::pair<SigBit, bool>> aiw_latches;
|
||||
dict<int, SigBit> aiw_inputs, aiw_inits;
|
||||
std::map<Wire*,int> mapping;
|
||||
};
|
||||
|
||||
struct SimPass : public Pass {
|
||||
SimPass() : Pass("sim", "simulate the circuit") { }
|
||||
void help() override
|
||||
|
|
@ -1268,6 +1411,13 @@ struct SimPass : public Pass {
|
|||
log(" -fst <filename>\n");
|
||||
log(" write the simulation results to the given FST file\n");
|
||||
log("\n");
|
||||
log(" -aiw <filename>\n");
|
||||
log(" write the simulation results to an AIGER witness file\n");
|
||||
log(" (requires a *.aim file via -map)\n");
|
||||
log("\n");
|
||||
log(" -x\n");
|
||||
log(" ignore constant x outputs in simulation file.\n");
|
||||
log("\n");
|
||||
log(" -clock <portname>\n");
|
||||
log(" name of top-level clock input\n");
|
||||
log("\n");
|
||||
|
|
@ -1345,13 +1495,19 @@ struct SimPass : public Pass {
|
|||
if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
|
||||
std::string vcd_filename = args[++argidx];
|
||||
rewrite_filename(vcd_filename);
|
||||
worker.vcdfile.open(vcd_filename.c_str());
|
||||
worker.outputfiles.emplace_back(std::unique_ptr<VCDWriter>(new VCDWriter(&worker, vcd_filename.c_str())));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-fst" && argidx+1 < args.size()) {
|
||||
std::string fst_filename = args[++argidx];
|
||||
rewrite_filename(fst_filename);
|
||||
worker.fstfile = (struct fstContext *)fstWriterCreate(fst_filename.c_str(),1);
|
||||
worker.outputfiles.emplace_back(std::unique_ptr<FSTWriter>(new FSTWriter(&worker, fst_filename.c_str())));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-aiw" && argidx+1 < args.size()) {
|
||||
std::string aiw_filename = args[++argidx];
|
||||
rewrite_filename(aiw_filename);
|
||||
worker.outputfiles.emplace_back(std::unique_ptr<AIWWriter>(new AIWWriter(&worker, aiw_filename.c_str())));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-n" && argidx+1 < args.size()) {
|
||||
|
|
@ -1447,6 +1603,10 @@ struct SimPass : public Pass {
|
|||
worker.sim_mode = SimulationMode::gate;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-x") {
|
||||
worker.ignore_x = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
|
|||
Loading…
Reference in New Issue