mirror of https://github.com/YosysHQ/yosys.git
Claire Xen
GitHub
commit
2ca69e1b88
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@ -65,6 +65,20 @@ static double stringToTime(std::string str)
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return value * pow(10.0, g_units.at(endptr));
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}
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struct SimWorker;
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struct OutputWriter
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{
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OutputWriter(SimWorker *w) { worker = w;};
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virtual ~OutputWriter() {};
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virtual void write_header() = 0;
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virtual void write_step_header(int t) = 0;
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virtual void enter_scope(IdString) {};
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virtual void exit_scope() {};
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virtual void register_signal(Wire *, int) {};
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virtual void write_value(int, Const&) {};
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SimWorker *worker;
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};
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struct SimShared
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{
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bool debug = false;
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@ -77,6 +91,7 @@ struct SimShared
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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std::vector<std::unique_ptr<OutputWriter>> outputfiles;
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};
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void zinit(State &v)
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@ -140,8 +155,7 @@ struct SimInstance
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std::vector<Mem> memories;
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dict<Wire*, pair<int, Const>> vcd_database;
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dict<Wire*, pair<fstHandle, Const>> fst_database;
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dict<Wire*, pair<int, Const>> signal_database;
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dict<Wire*, fstHandle> fst_handles;
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SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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@ -685,28 +699,29 @@ struct SimInstance
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it.second->writeback(wbmods);
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}
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void write_vcd_header(std::ofstream &f, int &id)
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void write_output_header(OutputWriter *writer, int &id)
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{
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f << stringf("$scope module %s $end\n", log_id(name()));
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writer->enter_scope(name());
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for (auto wire : module->wires())
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{
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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f << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
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vcd_database[wire] = make_pair(id++, Const());
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signal_database[wire] = make_pair(id, Const());
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writer->register_signal(wire, id);
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id++;
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}
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for (auto child : children)
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child.second->write_vcd_header(f, id);
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child.second->write_output_header(writer, id);
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f << stringf("$upscope $end\n");
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writer->exit_scope();
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}
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void write_vcd_step(std::ofstream &f)
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void write_output_step_values()
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{
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for (auto &it : vcd_database)
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for (auto &it : signal_database)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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@ -717,68 +732,12 @@ struct SimInstance
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it.second.second = value;
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f << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: f << "0"; break;
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case State::S1: f << "1"; break;
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case State::Sx: f << "x"; break;
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default: f << "z";
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}
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}
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f << stringf(" n%d\n", id);
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for(auto& writer : shared->outputfiles)
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writer->write_value(id, value);
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}
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for (auto child : children)
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child.second->write_vcd_step(f);
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}
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void write_fst_header(struct fstContext *f)
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{
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fstWriterSetScope(f, FST_ST_VCD_MODULE, stringf("%s",log_id(name())).c_str(), nullptr);
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for (auto wire : module->wires())
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{
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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fstHandle id = fstWriterCreateVar(f, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
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stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
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fst_database[wire] = make_pair(id, Const());
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}
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for (auto child : children)
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child.second->write_fst_header(f);
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fstWriterSetUpscope(f);
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}
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void write_fst_step(struct fstContext *f)
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{
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for (auto &it : fst_database)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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fstHandle id = it.second.first;
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if (it.second.second == value)
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continue;
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it.second.second = value;
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std::stringstream ss;
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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}
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}
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fstWriterEmitValueChange(f, id, ss.str().c_str());
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}
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for (auto child : children)
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child.second->write_fst_step(f);
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child.second->write_output_step_values();
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}
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void setInitState()
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@ -857,11 +816,7 @@ struct SimInstance
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struct SimWorker : SimShared
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{
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SimInstance *top = nullptr;
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std::ofstream vcdfile, aiwfile;
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struct fstContext *fstfile = nullptr;
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pool<IdString> clock, clockn, reset, resetn;
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dict<int, std::pair<SigBit, bool>> aiw_latches;
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dict<int, SigBit> aiw_inputs, aiw_inits;
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std::string timescale;
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std::string sim_filename;
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std::string map_filename;
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@ -869,150 +824,24 @@ struct SimWorker : SimShared
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~SimWorker()
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{
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outputfiles.clear();
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delete top;
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}
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void write_vcd_header()
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{
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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std::time_t t = std::time(nullptr);
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char mbstr[255];
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if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
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vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
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}
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if (!timescale.empty())
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vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
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int id = 1;
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top->write_vcd_header(vcdfile, id);
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vcdfile << stringf("$enddefinitions $end\n");
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}
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void write_vcd_step(int t)
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{
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vcdfile << stringf("#%d\n", t);
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top->write_vcd_step(vcdfile);
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}
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void write_fst_header()
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{
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std::time_t t = std::time(nullptr);
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fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
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fstWriterSetVersion(fstfile, yosys_version_str);
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if (!timescale.empty())
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fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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top->write_fst_header(fstfile);
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}
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void write_fst_step(int t)
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{
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fstWriterEmitTimeChange(fstfile, t);
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top->write_fst_step(fstfile);
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}
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void write_aiw_header()
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{
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std::ifstream mf(map_filename);
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std::string type, symbol;
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int variable, index;
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while (mf >> type >> variable >> index >> symbol) {
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RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
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Wire *w = top->module->wire(escaped_s);
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if (!w)
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log_error("Wire %s not present in module %s\n",log_signal(w),log_id(top->module));
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if (index < w->start_offset || index > w->start_offset + w->width)
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log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
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if (type == "input") {
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aiw_inputs[variable] = SigBit(w,index);
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} else if (type == "init") {
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aiw_inits[variable] = SigBit(w,index);
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} else if (type == "latch") {
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aiw_latches[variable] = {SigBit(w,index), false};
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} else if (type == "invlatch") {
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aiw_latches[variable] = {SigBit(w,index), true};
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}
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}
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for (int i = 0;; i++)
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{
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if (aiw_latches.count(i)) {
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auto v = top->get_state(aiw_latches.at(i).first);
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if (v == State::S1)
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aiwfile << (aiw_latches.at(i).second ? '0' : '1');
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else
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aiwfile << (aiw_latches.at(i).second ? '1' : '0');
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continue;
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}
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aiwfile << '\n';
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break;
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}
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}
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void write_aiw_step()
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{
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for (int i = 0;; i++)
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{
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if (aiw_inputs.count(i)) {
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auto v = top->get_state(aiw_inputs.at(i));
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if (v == State::S1)
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aiwfile << '1';
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else
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aiwfile << '0';
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continue;
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}
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if (aiw_inits.count(i)) {
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auto v = top->get_state(aiw_inits.at(i));
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if (v == State::S1)
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aiwfile << '1';
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else
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aiwfile << '0';
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continue;
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}
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aiwfile << '\n';
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break;
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}
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}
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void write_aiw_end()
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{
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aiwfile << '.' << '\n';
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}
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void write_output_header()
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{
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if (vcdfile.is_open())
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write_vcd_header();
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if (fstfile)
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write_fst_header();
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if (aiwfile.is_open())
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write_aiw_header();
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for(auto& writer : outputfiles)
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writer->write_header();
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}
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void write_output_step(int t)
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{
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if (vcdfile.is_open())
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write_vcd_step(t);
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if (fstfile)
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write_fst_step(t);
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if (aiwfile.is_open())
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write_aiw_step();
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for(auto& writer : outputfiles)
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writer->write_step_header(t);
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top->write_output_step_values();
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}
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void write_output_end()
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{
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if (fstfile)
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fstWriterClose(fstfile);
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if (aiwfile.is_open())
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write_aiw_end();
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}
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void update()
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{
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@ -1101,8 +930,6 @@ struct SimWorker : SimShared
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write_output_step(10*numcycles + 2);
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write_output_end();
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if (writeback) {
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pool<Module*> wbmods;
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top->writeback(wbmods);
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@ -1230,7 +1057,6 @@ struct SimWorker : SimShared
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} catch(fst_end_of_data_exception) {
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// end of data detected
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}
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write_output_end();
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if (writeback) {
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pool<Module*> wbmods;
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@ -1327,10 +1153,225 @@ struct SimWorker : SimShared
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}
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}
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write_output_step(10*cycle);
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write_output_end();
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}
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};
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struct VCDWriter : public OutputWriter
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{
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VCDWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
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vcdfile.open(filename.c_str());
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}
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void write_header() override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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std::time_t t = std::time(nullptr);
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char mbstr[255];
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if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
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vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
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}
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if (!worker->timescale.empty())
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vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str());
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int id = 1;
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worker->top->write_output_header(this, id);
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vcdfile << stringf("$enddefinitions $end\n");
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}
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void write_step_header(int t) override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << stringf("#%d\n", t);
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}
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void enter_scope(IdString name) override
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{
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vcdfile << stringf("$scope module %s $end\n", log_id(name));
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}
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void exit_scope() override
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{
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vcdfile << stringf("$upscope $end\n");
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}
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void register_signal(Wire *wire, int id) override
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{
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vcdfile << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
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}
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void write_value(int id, Const& value) override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: vcdfile << "0"; break;
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case State::S1: vcdfile << "1"; break;
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case State::Sx: vcdfile << "x"; break;
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default: vcdfile << "z";
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}
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}
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vcdfile << stringf(" n%d\n", id);
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}
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std::ofstream vcdfile;
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};
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struct FSTWriter : public OutputWriter
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{
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FSTWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
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fstfile = (struct fstContext *)fstWriterCreate(filename.c_str(),1);
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}
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virtual ~FSTWriter()
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{
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fstWriterClose(fstfile);
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}
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void write_header() override
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{
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if (!fstfile) return;
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std::time_t t = std::time(nullptr);
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fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
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fstWriterSetVersion(fstfile, yosys_version_str);
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if (!worker->timescale.empty())
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fstWriterSetTimescaleFromString(fstfile, worker->timescale.c_str());
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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int id = 1;
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worker->top->write_output_header(this, id);
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}
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void write_step_header(int t) override
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{
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if (!fstfile) return;
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fstWriterEmitTimeChange(fstfile, t);
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}
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void enter_scope(IdString name) override
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{
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fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr);
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}
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void exit_scope() override
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{
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fstWriterSetUpscope(fstfile);
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}
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void register_signal(Wire *wire, int id) override
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{
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fstHandle fst_id = fstWriterCreateVar(fstfile, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
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stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
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mapping.emplace(id, fst_id);
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}
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void write_value(int id, Const& value) override
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{
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if (!fstfile) return;
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std::stringstream ss;
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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}
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}
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fstWriterEmitValueChange(fstfile, mapping[id], ss.str().c_str());
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}
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struct fstContext *fstfile = nullptr;
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std::map<int,fstHandle> mapping;
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};
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struct AIWWriter : public OutputWriter
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{
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AIWWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
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aiwfile.open(filename.c_str());
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}
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virtual ~AIWWriter()
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||||
{
|
||||
aiwfile << '.' << '\n';
|
||||
}
|
||||
|
||||
void write_header() override
|
||||
{
|
||||
if (!aiwfile.is_open()) return;
|
||||
std::ifstream mf(worker->map_filename);
|
||||
std::string type, symbol;
|
||||
int variable, index;
|
||||
while (mf >> type >> variable >> index >> symbol) {
|
||||
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
|
||||
Wire *w = worker->top->module->wire(escaped_s);
|
||||
if (!w)
|
||||
log_error("Wire %s not present in module %s\n",log_signal(w),log_id(worker->top->module));
|
||||
if (index < w->start_offset || index > w->start_offset + w->width)
|
||||
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
|
||||
if (type == "input") {
|
||||
aiw_inputs[variable] = SigBit(w,index);
|
||||
} else if (type == "init") {
|
||||
aiw_inits[variable] = SigBit(w,index);
|
||||
} else if (type == "latch") {
|
||||
aiw_latches[variable] = {SigBit(w,index), false};
|
||||
} else if (type == "invlatch") {
|
||||
aiw_latches[variable] = {SigBit(w,index), true};
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0;; i++)
|
||||
{
|
||||
if (aiw_latches.count(i)) {
|
||||
auto v = worker->top->get_state(aiw_latches.at(i).first);
|
||||
if (v == State::S1)
|
||||
aiwfile << (aiw_latches.at(i).second ? '0' : '1');
|
||||
else
|
||||
aiwfile << (aiw_latches.at(i).second ? '1' : '0');
|
||||
continue;
|
||||
}
|
||||
aiwfile << '\n';
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void write_step_header(int) override
|
||||
{
|
||||
if (!aiwfile.is_open()) return;
|
||||
for (int i = 0;; i++)
|
||||
{
|
||||
if (aiw_inputs.count(i)) {
|
||||
auto v = worker->top->get_state(aiw_inputs.at(i));
|
||||
if (v == State::S1)
|
||||
aiwfile << '1';
|
||||
else
|
||||
aiwfile << '0';
|
||||
continue;
|
||||
}
|
||||
if (aiw_inits.count(i)) {
|
||||
auto v = worker->top->get_state(aiw_inits.at(i));
|
||||
if (v == State::S1)
|
||||
aiwfile << '1';
|
||||
else
|
||||
aiwfile << '0';
|
||||
continue;
|
||||
}
|
||||
aiwfile << '\n';
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
std::ofstream aiwfile;
|
||||
dict<int, std::pair<SigBit, bool>> aiw_latches;
|
||||
dict<int, SigBit> aiw_inputs, aiw_inits;
|
||||
};
|
||||
|
||||
struct SimPass : public Pass {
|
||||
SimPass() : Pass("sim", "simulate the circuit") { }
|
||||
void help() override
|
||||
|
|
@ -1428,19 +1469,19 @@ struct SimPass : public Pass {
|
|||
if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
|
||||
std::string vcd_filename = args[++argidx];
|
||||
rewrite_filename(vcd_filename);
|
||||
worker.vcdfile.open(vcd_filename.c_str());
|
||||
worker.outputfiles.emplace_back(std::unique_ptr<VCDWriter>(new VCDWriter(&worker, vcd_filename.c_str())));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-fst" && argidx+1 < args.size()) {
|
||||
std::string fst_filename = args[++argidx];
|
||||
rewrite_filename(fst_filename);
|
||||
worker.fstfile = (struct fstContext *)fstWriterCreate(fst_filename.c_str(),1);
|
||||
worker.outputfiles.emplace_back(std::unique_ptr<FSTWriter>(new FSTWriter(&worker, fst_filename.c_str())));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-aiw" && argidx+1 < args.size()) {
|
||||
std::string aiw_filename = args[++argidx];
|
||||
rewrite_filename(aiw_filename);
|
||||
worker.aiwfile.open(aiw_filename.c_str());
|
||||
worker.outputfiles.emplace_back(std::unique_ptr<AIWWriter>(new AIWWriter(&worker, aiw_filename.c_str())));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-n" && argidx+1 < args.size()) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue