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65 Commits

Author SHA1 Message Date
gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-17 21:07:20 +00:00
Pepijn de Vos f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
Konrad Beckmann 5b9a975eba synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Dan Ravensloft 7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Marcelina Kościelnicka 90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init 
gowin: Fix INIT values in sim library.
 2020-07-05 12:02:31 +02:00
Marcelina Kościelnicka 9beed4d771 gowin: Fix INIT values in sim library. 2020-07-05 03:03:48 +02:00
Dan Ravensloft 01772dec8c gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
whitequark 26cda3c247 gowin,ecp5: remove generated files in `make clean`. 2020-04-24 23:26:39 +00:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Diego H 87883f6d88 Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
Eddie Hung 0b0148399c synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
whitequark f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming 
Harmonize BRAM/LUTRAM descriptions across all of Yosys
 2020-01-02 21:06:17 +00:00
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys. 
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
 2020-01-01 12:30:00 +00:00
Eddie Hung c9e3b26412 Disable synth_gowin -abc9 as it offers no advantages yet 2019-12-30 13:28:29 -08:00
Eddie Hung aa6d06c1b5 Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" 
This reverts commit 6008bb7002.
 2019-12-30 13:28:29 -08:00
Pepijn de Vos a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
Pepijn de Vos 72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos 6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Marcin Kościelnicki 1d098b7195 gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Pepijn de Vos 8ab412eb16 Remove dff init altogether 
The hardware does not actually support it.
In reality it is always initialised to its reset value.
 2019-11-19 15:53:44 +01:00
Pepijn de Vos dd8c7e1ddd add help for nowidelut and abc9 options 2019-11-18 14:26:09 +01:00
Pepijn de Vos ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Pepijn de Vos 0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Pepijn de Vos 0f6269b04c add IOBUF 2019-10-28 15:33:05 +01:00
Pepijn de Vos 903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos 2f5e9e9885 More formatting 2019-10-28 13:10:12 +01:00
Pepijn de Vos c1921b4561 really really fix formatting maybe 2019-10-28 13:01:20 +01:00
Pepijn de Vos 293b2c2de5 undo formatting fuckup 2019-10-28 12:57:12 +01:00
Pepijn de Vos f88335a8a5 add wide luts 2019-10-28 12:49:08 +01:00
Pepijn de Vos 5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Pepijn de Vos 8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Pepijn de Vos 03457ee13e add a few more missing dff 2019-10-21 16:08:13 +02:00
Pepijn de Vos 8a2699c40c add negedge DFF 2019-10-21 12:31:11 +02:00
Pepijn de Vos af7bdd598e use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
Pepijn de Vos 72323e11a4 remove duplicate DFFR 2019-10-16 11:24:56 +02:00
Pepijn de Vos 2fb20f184a Revert "add MUX support" 
It turns out that they make everything worse and they don't PnR.

This reverts commit 3eff2271d0.
 2019-09-06 11:28:17 +02:00
Pepijn de Vos 96efa63f16 fix BRAM width and init 2019-09-06 10:55:04 +02:00
Pepijn de Vos 1b9f7f49b5 add more DFF to sim lib 2019-09-06 09:01:07 +02:00
Pepijn de Vos 5168b6ffa4 WIP aditional DFF primitives 2019-09-05 19:12:47 +02:00
Pepijn de Vos 47374a495d support bram initialisation 2019-09-05 17:25:51 +02:00
Pepijn de Vos 7a43be5e43 use singleton ground and vcc nets, apparently this makes pnr happier 2019-09-05 16:38:47 +02:00
Pepijn de Vos 3eff2271d0 add MUX support 2019-09-05 13:36:41 +02:00
Pepijn de Vos ae93c034ad set undriven pads to zero 2019-09-04 16:29:40 +02:00