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11529 Commits

Author SHA1 Message Date
Claire Xenia Wolf 89df26e4bc Add optimization to rtlil back-end for all-x parameter values 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-27 16:02:20 +02:00
github-actions[bot] 1cac671c70 Bump version 2021-09-25 00:51:53 +00:00
Claire Xen 0146d83ed8
Merge pull request #3014 from YosysHQ/claire/fix-vgtest 
Fix "make vgtest"
 2021-09-24 17:50:34 +02:00
Zachary Snow 9658d2e337 Fix TOK_ID memory leak in for_initialization 2021-09-23 13:33:55 -04:00
Claire Xenia Wolf 15fb0107dc Fix "make vgtest" so it runs to the end (but now it fails ;) 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-23 14:54:28 +02:00
github-actions[bot] 9432400ec8 Bump version 2021-09-22 00:54:54 +00:00
Zachary Snow d6fe6d4fb6 sv: support wand and wor of data types 
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
 2021-09-21 14:52:28 -04:00
Zachary Snow 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues 
- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
 2021-09-21 12:10:59 -04:00
github-actions[bot] 3931b3a03f Bump version 2021-09-19 00:52:56 +00:00
Miodrag Milanović e6766b950c
Merge pull request #3010 from the6p4c/master 
Fix protobuf backend build dependencies - intermittent build issue due to missing rule
 2021-09-18 09:16:58 +02:00
the6p4c c25122e339 Fix protobuf backend build dependencies 
backends/protobuf/protobuf.cc depends on the source and header files
generated by protoc, but this dependency wasn't explicitly declared. Add
a rule to the Makefile to fix intermittent build failures when the
protobuf header/source file isn't built before protobuf.cc.
 2021-09-17 13:36:39 +10:00
github-actions[bot] c88eaea6e0 Bump version 2021-09-14 00:56:06 +00:00
Marcelina Kościelnicka 551ef85cd7 verilog: Squash flex-triggered warning. 2021-09-13 18:58:17 +02:00
Miodrag Milanović 1d52c07e9b
Updates for CHANGELOG (#2997) 
Added missing changes from git log and  group items
 2021-09-13 16:25:42 +02:00
github-actions[bot] f44110c625 Bump version 2021-09-11 00:50:11 +00:00
Miodrag Milanović 396918cc30
Merge pull request #3001 from YosysHQ/claire/sigcheck 
Add additional check to SigSpec
 2021-09-10 17:32:04 +02:00
Claire Xenia Wolf 4708907be8 Add additional check to SigSpec 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-10 16:51:34 +02:00
Marcelina Kościelnicka 33749f1e3a yosys-smtbmc: Fix reused loop variable. 
Fixes #2999.
 2021-09-10 13:34:58 +02:00
github-actions[bot] 1d61a911b7 Bump version 2021-09-10 00:55:14 +00:00
Eddie Hung 96b6410dcb
abc9: make re-entrant (#2993) 
* Add testcase

* Cleanup some state at end of abc9

* Re-assign abc9_box_id from scratch

* Suppress delete unless prep_bypass did something
 2021-09-09 10:06:31 -07:00
Eddie Hung 65316ec926
abc9: holes module to instantiate cells with NEW_ID (#2992) 
* Add testcase

* holes module to instantiate cells with NEW_ID
 2021-09-09 10:06:20 -07:00
Eddie Hung f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991) 
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
 2021-09-09 10:05:55 -07:00
github-actions[bot] 50be8fd0c2 Bump version 2021-09-03 00:50:30 +00:00
Miodrag Milanovic c3d4bb4cc9 update required verific version 2021-09-02 14:59:16 +02:00
github-actions[bot] fe9da25c40 Bump version 2021-09-01 00:55:51 +00:00
Zachary Snow b2e9717419 sv: support declaration in generate for initialization 
This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
 2021-08-31 12:34:55 -06:00
github-actions[bot] b20bb653ce Bump version 2021-08-31 00:51:55 +00:00
Zachary Snow f0a52e3dd2 sv: support declaration in procedural for initialization 
In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
 2021-08-30 15:19:21 -06:00
github-actions[bot] 1dbf91a8ef Bump version 2021-08-30 00:49:03 +00:00
kittennbfive 6de500ec08
[ECP5] fix wrong link for syn_* attributes description (#2984) 2021-08-29 11:45:23 +02:00
github-actions[bot] 591fe72203 Bump version 2021-08-23 00:46:01 +00:00
ECP5-PCIe dfc453b246 Add DLLDELD 2021-08-22 18:48:44 +02:00
Marcelina Kościelnicka 9cbff3a4a9 opt_merge: Remove and reinsert init when connecting nets. 
Mutating the SigMap by adding a new connection will throw off FfInitVals
index.  Work around this by removing the relevant init values from index
whenever we connect nets, then re-add the new init value.

Should fix #2920.
 2021-08-22 18:34:11 +02:00
Marcelina Kościelnicka 62d41d4639 opt_clean: Make the init attribute follow the FF's Q. 
Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
 2021-08-22 15:38:29 +02:00
github-actions[bot] 21e710eb55 Bump version 2021-08-21 00:48:23 +00:00
Pepijn de Vos c2d358484f
Gowin: deal with active-low tristate (#2971) 
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
 2021-08-20 21:21:06 +02:00
Miodrag Milanović c2866780d2
Merge pull request #2973 from YosysHQ/micko/optional_extensions 
Make Verific extensions optional
 2021-08-20 16:09:55 +02:00
Miodrag Milanovic b59c427348 Make Verific extensions optional 2021-08-20 10:19:04 +02:00
github-actions[bot] 75a4cdfc8a Bump version 2021-08-18 00:51:20 +00:00
Sylvain Munaut 3806b07303 ice40: Fix typo in SB_CARRY specify for LP/UltraPlus 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-17 14:33:30 +02:00
github-actions[bot] e6dd4db0af Bump version 2021-08-17 00:49:33 +00:00
Marcelina Kościelnicka 10f8b75dca kernel/mem: Remove old parameter when upgrading $mem to $mem_v2. 
Fixes #2967.
 2021-08-16 13:31:27 +02:00
github-actions[bot] 83c0f82dc8 Bump version 2021-08-15 00:50:04 +00:00
Marcelina Kościelnicka faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 
Fixes #2962.
 2021-08-14 15:26:11 +02:00
github-actions[bot] 539d4ee907 Bump version 2021-08-14 00:46:42 +00:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs 
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
 2021-08-13 17:11:35 -06:00
Marcelina Kościelnicka f791328506 Add opt_mem_widen pass. 
If all of us are wide, then none of us are!
 2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka 1f74ec3535 memory_share: Add -nosat and -nowiden options. 
This unlocks wide port recognition by default.
 2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka 9fdedf4d1c memory_dff: Recognize soft transparency logic. 2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka 616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00