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13756 Commits

Author SHA1 Message Date
Catherine ddf7b46955 fmt,cxxrtl: fix printing of non-decimal signed numbers. 
Also fix interaction of `NUMERIC` justification with `show_base`.
 2024-04-02 12:13:22 +02:00
Catherine 00c5b60dfd fmt,cxxrtl: add option to group digits in numbers. 
The option is serialized to RTLIL as `_` (to match Python's option with
the same symbol), and sets the `group` flag. This flag inserts an `_`
symbol between each group of 3 digits (for decimal) or four digits (for
binary, hex, and octal).
 2024-04-02 12:13:22 +02:00
Catherine 7b94599162 fmt,cxxrtl: add option to print numeric base (`0x`, etc). 
The option is serialized to RTLIL as `#` (to match Python's and Rust's
option with the same symbol), and sets the `show_base` flag. Because
the flag is called `show_base` and not e.g. `alternate_format` (which
is what Python and Rust call it), in addition to the prefixes `0x`,
`0X`, `0o`, `0b`, the RTLIL option also prints the `0d` prefix.
 2024-04-02 12:13:22 +02:00
Catherine bf5a960668 fmt,cxxrtl: add `UNICHAR` format type. 
This format type is used to print an Unicode character (code point) as
its UTF-8 serialization. To this end, two UTF-8 decoders (one for fmt,
one for cxxrtl) are added for rendering. When converted to a Verilog
format specifier, `UNICHAR` degrades to `%c` with the low 7 bits of
the code point, which has equivalent behavior for inputs not exceeding
ASCII. (SystemVerilog leaves source and display encodings completely
undefined.)
 2024-04-02 12:13:22 +02:00
Catherine 1780e2eb1e fmt,cxxrtl: add support for `NUMERIC` justification. 
Before this commit, the existing alignments were `LEFT` and `RIGHT`,
which added the `padding` character to the right and left just before
finishing formatting. However, if `padding == '0'` and the alignment is
to the right, then the padding character (digit zero) was added after
the sign, if one is present.

After this commit, the special case for `padding == '0'` is removed,
and the new justification `NUMERIC` adds the padding character like
the justification `RIGHT`, except after the sign, if one is present.
(Space, for the `SPACE_MINUS` sign mode, counts as the sign.)
 2024-04-02 12:13:22 +02:00
Catherine 6d6b138607 fmt,cxxrtl: support `{,PLUS_,SPACE_}MINUS` integer formats. 
The first two were already supported with the `plus` boolean flag.
The third one is a new specifier, which is allocated the ` ` character.
In addition, `MINUS` is now allocated the `-` character, but old format
where there is no `+`, `-`, or `-` in the respective position is also
accepted for compatibility.
 2024-04-02 12:13:22 +02:00
Catherine 8388846e3a fmt,cxxrtl: add support for uppercase hex format. 
This is necessary for translating Python format strings in Amaranth.
 2024-04-02 12:13:22 +02:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`. 
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
 2024-04-02 12:13:22 +02:00
Martin Povišer 0210509dea
Merge pull request #4309 from widlarizer/emil/fix-code-style-link 
docs: Update linux kernel coding style link
 2024-04-02 11:29:36 +02:00
Emil J. Tywoniak 73cacd543c docs: Update linux kernel coding style link 2024-04-02 11:23:56 +02:00
github-actions[bot] b9d3bffda5 Bump version 2024-03-31 00:18:11 +00:00
Merry d07a55a852 cxxrtl: Fix sdivmod 
x = x.neg(); results in the subsequent x.is_neg() always being false.
Ditto for the dividend.is_neg() != divisor.is_neg() test.
 2024-03-30 07:56:11 +00:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Martin Povišer bc087f91ed techmap: Fix using overwritten results in Kogge-Stone 2024-03-27 18:32:25 +01:00
Martin Povišer c49d6e7874 techmap: Add Kogge-Stone test 2024-03-27 11:08:26 +01:00
Martin Povišer 4570d064e5 techmap: Split out Kogge-Stone into a separate file 2024-03-27 11:07:24 +01:00
github-actions[bot] 0a854cf4ce Bump version 2024-03-26 00:15:18 +00:00
N. Engelhardt c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges 
Use cell edges data in `check`, improve messages
 2024-03-25 16:19:35 +01:00
Miodrag Milanović c9d9b9ec2c
Merge pull request #4270 from YosysHQ/krys/config-none 
Change default CONFIG to none
 2024-03-25 16:13:32 +01:00
N. Engelhardt 6248d5901b
Merge pull request #4297 from chenrui333/fix-master-branch-refs 
chore: fix master branch refs
 2024-03-25 16:01:33 +01:00
Martin Povišer c38201e15d techmap: Add a Kogge-Stone option for `$lcu` mapping 2024-03-25 14:56:17 +01:00
Rui Chen b57a803f60
chore: fix master branch refs 
Signed-off-by: Rui Chen <rui@chenrui.dev>
 2024-03-24 00:41:54 -04:00
Peter Gadfort 160e3e089a add port statistics to stat command 2024-03-22 09:20:20 -04:00
Miodrag Milanovic 4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
github-actions[bot] d73f71e813 Bump version 2024-03-19 00:20:31 +00:00
Krystine Sherwin c6795cefc5
docs: Install python requirements 2024-03-19 06:05:03 +13:00
Krystine Sherwin f72ddfb09d docs: Fix repo file links 2024-03-19 05:57:26 +13:00
Krystine Sherwin 29c8a3bef9 docs: Fix splice.v in verific 2024-03-19 05:57:26 +13:00
N. Engelhardt 3f54bf102c
Merge pull request #3907 from YosysHQ/krys/docs 
Manual rewrite and presentation merge
 2024-03-18 17:12:57 +01:00
Miodrag Milanovic 9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Krystine Sherwin ff10aeebd6
Fix some synth_* help messages 
Mostly memory_libmap arg checks; puts the checks into an else block on the `if (help_mode)` check to avoid cases like `synth_ice40` listing `-no-auto-huge [-no-auto-huge]`.
Also fix `map_iopad` section being empty in `synth_fabulous`.
 2024-03-18 11:33:18 +13:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Krystine Sherwin 49f1bea1d2
docs: Add synth_ice40 to macro checks 2024-03-18 11:01:09 +13:00
Krystine Sherwin b6ffdec2ce
docs: Update OSS CAD suite info 2024-03-18 10:45:31 +13:00
Krystine Sherwin d2bf5a83af
Merge branch 'origin/master' into krys/docs 2024-03-18 10:39:30 +13:00
Krystine Sherwin 2832034877
docs: Clarify install instructions 
`config-clang` is the default, and doesn't need to be run first.  Previous instructions were ambiguous about that point.
Add note on using a different `CXX`.
 2024-03-18 10:35:01 +13:00
Krystine Sherwin bc9cccacf2
docs: Move fifo localparams into module def 
Fix for failing CI.
 2024-03-18 10:02:40 +13:00
github-actions[bot] 3231c1cd93 Bump version 2024-03-16 00:14:56 +00:00
N. Engelhardt 584692d53c
Merge pull request #4281 from YosysHQ/cat/issue-template-wasm 
Add WebAssembly as a platform to `ISSUE_TEMPLATE/bug_report.yml`
 2024-03-15 10:01:26 +01:00
Miodrag Milanovic 7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Catherine 29e3e10378
Add WebAssembly as a platform to ISSUE_TEMPLATE/bug_report.yml. 2024-03-13 10:04:13 +00:00
github-actions[bot] b3124f30e4 Bump version 2024-03-13 00:15:33 +00:00
Miodrag Milanovic 18cec2d9a9 Next dev cycle 2024-03-12 08:57:48 +01:00
Miodrag Milanovic 00338082b0 Release version 0.39 2024-03-12 08:55:10 +01:00
github-actions[bot] 0944664e60 Bump version 2024-03-12 00:15:21 +00:00
Krystine Sherwin 643c9540da
Makefile: reorder CONFIG=none check 2024-03-12 09:39:25 +13:00
Krystine Sherwin e0389436da
Makefile: Remove narrowing from ABCMKARGS 2024-03-12 09:18:38 +13:00
N. Engelhardt 0909c2ef5e
Merge pull request #4268 from jix/smtbmc-track-assumes 
smtbmc: Add --track-assumes and --minimize-assumes options
 2024-03-11 16:34:30 +01:00