mirror of https://github.com/YosysHQ/yosys.git
fmt,cxxrtl: add option to group digits in numbers.
The option is serialized to RTLIL as `_` (to match Python's option with the same symbol), and sets the `group` flag. This flag inserts an `_` symbol between each group of 3 digits (for decimal) or four digits (for binary, hex, and octal).
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@ -1042,6 +1042,7 @@ struct fmt_part {
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} sign; // = MINUS;
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bool hex_upper; // = false;
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bool show_base; // = false;
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bool group; // = false;
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// VLOG_TIME type
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bool realtime; // = false;
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@ -1104,13 +1105,19 @@ struct fmt_part {
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}
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if (base == 2) {
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for (size_t index = 0; index < width; index++) {
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if (group && index > 0 && index % 4 == 0)
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buf += '_';
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buf += (val.bit(index) ? '1' : '0');
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}
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if (show_base)
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buf += "0b";
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for (size_t i = width; i > 0; i--)
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buf += (val.bit(i - 1) ? '1' : '0');
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buf += "b0";
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std::reverse(buf.begin(), buf.end());
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} else if (base == 8 || base == 16) {
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size_t step = (base == 16) ? 4 : 3;
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for (size_t index = 0; index < width; index += step) {
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if (group && index > 0 && index % (4 * step) == 0)
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buf += '_';
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uint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);
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if (step == 4)
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value |= val.bit(index + 3) << 3;
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@ -1126,7 +1133,10 @@ struct fmt_part {
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if (val.is_zero())
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buf += '0';
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value<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();
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size_t index = 0;
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while (!xval.is_zero()) {
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if (group && index > 0 && index % 3 == 0)
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buf += '_';
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value<(Bits > 4 ? Bits : 4)> quotient, remainder;
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if (Bits >= 4)
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std::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});
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@ -1134,6 +1144,7 @@ struct fmt_part {
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std::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);
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buf += '0' + remainder.template trunc<4>().template get<uint8_t>();
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xval = quotient;
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index++;
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}
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if (show_base)
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buf += "d0";
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@ -156,6 +156,10 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
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part.show_base = true;
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++i;
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}
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if (fmt[i] == '_') {
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part.group = true;
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++i;
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}
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if (fmt[i] == 'u')
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part.signed_ = false;
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@ -241,6 +245,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
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case FmtPart::SPACE_MINUS: fmt += ' '; break;
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}
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fmt += part.show_base ? "#" : "";
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fmt += part.group ? "_" : "";
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fmt += part.signed_ ? 's' : 'u';
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} else if (part.type == FmtPart::STRING) {
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fmt += 'c';
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@ -683,6 +688,7 @@ void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(c
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os << ", ";
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os << part.hex_upper << ", ";
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os << part.show_base << ", ";
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os << part.group << ", ";
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os << part.realtime;
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os << " }.render(";
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emit_sig(part.sig);
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@ -737,12 +743,27 @@ std::string Fmt::render() const
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}
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if (part.base == 2) {
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for (size_t index = 0; index < (size_t)value.size(); index++) {
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if (part.group && index > 0 && index % 4 == 0)
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buf += '_';
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RTLIL::State bit = value[index];
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if (bit == State::Sx)
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buf += 'x';
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else if (bit == State::Sz)
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buf += 'z';
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else if (bit == State::S1)
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buf += '1';
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else /* if (bit == State::S0) */
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buf += '0';
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}
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if (part.show_base)
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buf += "0b";
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buf = value.as_string();
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buf += "b0";
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std::reverse(buf.begin(), buf.end());
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} else if (part.base == 8 || part.base == 16) {
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size_t step = (part.base == 16) ? 4 : 3;
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for (size_t index = 0; index < (size_t)value.size(); index += step) {
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if (part.group && index > 0 && index % (4 * step) == 0)
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buf += '_';
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RTLIL::Const subvalue = value.extract(index, min(step, value.size() - index));
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bool has_x = false, all_x = true, has_z = false, all_z = true;
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for (State bit : subvalue) {
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@ -799,9 +820,13 @@ std::string Fmt::render() const
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log_assert(absvalue.is_fully_def());
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if (absvalue.is_fully_zero())
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buf += '0';
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size_t index = 0;
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while (!absvalue.is_fully_zero()) {
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if (part.group && index > 0 && index % 3 == 0)
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buf += '_';
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buf += '0' + RTLIL::const_mod(absvalue, 10, false, false, 4).as_int();
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absvalue = RTLIL::const_div(absvalue, 10, false, false, absvalue.size());
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index++;
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}
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if (part.show_base)
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buf += "d0";
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@ -85,6 +85,7 @@ struct FmtPart {
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} sign = MINUS;
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bool hex_upper = false;
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bool show_base = false;
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bool group = false;
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// VLOG_TIME type
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bool realtime = false;
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