diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 008401232..31085b745 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -1042,6 +1042,7 @@ struct fmt_part { } sign; // = MINUS; bool hex_upper; // = false; bool show_base; // = false; + bool group; // = false; // VLOG_TIME type bool realtime; // = false; @@ -1104,13 +1105,19 @@ struct fmt_part { } if (base == 2) { + for (size_t index = 0; index < width; index++) { + if (group && index > 0 && index % 4 == 0) + buf += '_'; + buf += (val.bit(index) ? '1' : '0'); + } if (show_base) - buf += "0b"; - for (size_t i = width; i > 0; i--) - buf += (val.bit(i - 1) ? '1' : '0'); + buf += "b0"; + std::reverse(buf.begin(), buf.end()); } else if (base == 8 || base == 16) { size_t step = (base == 16) ? 4 : 3; for (size_t index = 0; index < width; index += step) { + if (group && index > 0 && index % (4 * step) == 0) + buf += '_'; uint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2); if (step == 4) value |= val.bit(index + 3) << 3; @@ -1126,7 +1133,10 @@ struct fmt_part { if (val.is_zero()) buf += '0'; value<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>(); + size_t index = 0; while (!xval.is_zero()) { + if (group && index > 0 && index % 3 == 0) + buf += '_'; value<(Bits > 4 ? Bits : 4)> quotient, remainder; if (Bits >= 4) std::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u}); @@ -1134,6 +1144,7 @@ struct fmt_part { std::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval); buf += '0' + remainder.template trunc<4>().template get(); xval = quotient; + index++; } if (show_base) buf += "d0"; diff --git a/kernel/fmt.cc b/kernel/fmt.cc index 8f4e61722..f5793d796 100644 --- a/kernel/fmt.cc +++ b/kernel/fmt.cc @@ -156,6 +156,10 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) { part.show_base = true; ++i; } + if (fmt[i] == '_') { + part.group = true; + ++i; + } if (fmt[i] == 'u') part.signed_ = false; @@ -241,6 +245,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const { case FmtPart::SPACE_MINUS: fmt += ' '; break; } fmt += part.show_base ? "#" : ""; + fmt += part.group ? "_" : ""; fmt += part.signed_ ? 's' : 'u'; } else if (part.type == FmtPart::STRING) { fmt += 'c'; @@ -683,6 +688,7 @@ void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function 0 && index % 4 == 0) + buf += '_'; + RTLIL::State bit = value[index]; + if (bit == State::Sx) + buf += 'x'; + else if (bit == State::Sz) + buf += 'z'; + else if (bit == State::S1) + buf += '1'; + else /* if (bit == State::S0) */ + buf += '0'; + } if (part.show_base) - buf += "0b"; - buf = value.as_string(); + buf += "b0"; + std::reverse(buf.begin(), buf.end()); } else if (part.base == 8 || part.base == 16) { size_t step = (part.base == 16) ? 4 : 3; for (size_t index = 0; index < (size_t)value.size(); index += step) { + if (part.group && index > 0 && index % (4 * step) == 0) + buf += '_'; RTLIL::Const subvalue = value.extract(index, min(step, value.size() - index)); bool has_x = false, all_x = true, has_z = false, all_z = true; for (State bit : subvalue) { @@ -799,9 +820,13 @@ std::string Fmt::render() const log_assert(absvalue.is_fully_def()); if (absvalue.is_fully_zero()) buf += '0'; + size_t index = 0; while (!absvalue.is_fully_zero()) { + if (part.group && index > 0 && index % 3 == 0) + buf += '_'; buf += '0' + RTLIL::const_mod(absvalue, 10, false, false, 4).as_int(); absvalue = RTLIL::const_div(absvalue, 10, false, false, absvalue.size()); + index++; } if (part.show_base) buf += "d0"; diff --git a/kernel/fmt.h b/kernel/fmt.h index 10b1711f1..2d4b24979 100644 --- a/kernel/fmt.h +++ b/kernel/fmt.h @@ -85,6 +85,7 @@ struct FmtPart { } sign = MINUS; bool hex_upper = false; bool show_base = false; + bool group = false; // VLOG_TIME type bool realtime = false;